ISP1581BD STEricsson, ISP1581BD Datasheet - Page 7

• Manufacturer Part Number: ISP1581BD
• Manufacturer: STEricsson

Specifications of ISP1581BD

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
9397 750 13462
Product data
Table 2:
Symbol
DIOR
DIOW
INTRQ
CS1
CS0
BUS_CONF/
DA0
MODE0
DA1
DA2
[5]
[5]
[5]
[5]
[5]
[1]
Pin description for LQFP64
Pin
14
15
16
17
18
19
20
21
Rev. 06 — 23 December 2004
Type
I/O
I/O
I
O
O
I/O
I/O
O
[2]
Description
DMA read strobe (programmable polarity); direction
depends on bit MASTER in the DMA Hardware register
(DMA slave: input, DMA master: output); see
Table
through a 10 k resistor
bidirectional pad; push pull output; 5 ns slew rate control;
TTL; 5 V tolerant.
DMA write strobe (programmable polarity); direction
depends on bit MASTER in the DMA Hardware register
(DMA slave: input, DMA master: output); see
Table
through a 10 k resistor
bidirectional pad; push pull output; 5 ns slew rate control;
TTL; 5 V tolerant.
interrupt request input from ATA/ATAPI peripheral
input pad; TTL with hysteresis; 5 V tolerant; internal
pull-down resistor.
chip select output for ATA/ATAPI device; see
Table 34
CMOS output; 5 ns slew rate control
chip select output for ATA/ATAPI device; see
Table 34
CMOS output; 5 ns slew rate control
during power-up: input to select the bus configuration;
see
0 — Split Bus mode; multiplexed 8-bit address/data bus on
AD[7:0], separate DMA data bus on DATA[15:0]
1 — Generic Processor mode; separate 8-bit address on
AD[7:0], 16-bit processor data bus on DATA[15:0]. DMA is
multiplexed on the processor bus as DATA[15:0].
normal operation: address output to select the task file
register of an ATA/ATAPI device.
bidirectional pad; push pull output; 5 ns slew rate control;
TTL; 5 V tolerant
during power-up: input to select the read/write strobe
functionality in generic processor mode; see
Table 34
0 — Motorola style: pin 26 is R/W and pin 27 is DS
1 — 8051 style: pin 26 is RD and pin 27 is WR
normal operation: address output to select the task file
register of an ATA/ATAPI device
bidirectional pad; push pull output; 5 ns slew rate control;
TTL; 5 V tolerant
address output to select the task file register of an
ATA/ATAPI device; see
CMOS output; 5 ns slew rate control
Table 33
36; when not in use, connect this pin to V
36; when not in use, connect this pin to V
…continued
and
Hi-Speed USB peripheral controller
Table 34
Table 33
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
and
Table 34
ISP1581
Table 33
Table 33
Table 33
Table 35
Table 35
CC(I/O)
CC(I/O)
[4]
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