USB97CFDC2-MV-01P Standard Microsystems (SMSC), USB97CFDC2-MV-01P Datasheet
USB97CFDC2-MV-01P
Specifications of USB97CFDC2-MV-01P
Related parts for USB97CFDC2-MV-01P
USB97CFDC2-MV-01P Summary of contents
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... Detects All Overrun and Underrun Conditions - Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption USB97CFDC2-MV-01X for 100 pin TQFP lead-free RoHS compliant package SMSC DS – USB97CFDC2-01 FEATURES Enhanced Digital Data Separator - 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data ...
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... REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SMSC DS – USB97CFDC2-01 Page 2 DATASHEET Rev. 02-27-07 ...
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... GENERAL DESCRIPTION The USB97CFDC2- integration of an Enhanced Multi-Endpoint USB 1.1 Peripheral Controller, a 32K Byte Program ROM, and the SMSC Floppy Disk Controller used in many of its Super IO products, such as the FDC37C869. Special care in the design has been taken to assure the lowest possible system current draw (<250µA) during SUSPEND mode operation ...
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... PIN CONFIGURATION...................................................................................................................................6 4 BLOCK DIAGRAM ..........................................................................................................................................7 5 PIN DESCRIPTIONS........................................................................................................................................8 5 UFFER YPE ESCRIPTIONS 6 CONFIGURATION OPTIONS......................................................................................................................12 7 BOARD TEST MODE OPERATION ........................................................................................................... PARAMETERS......................................................................................................................................... PARAMETERS.........................................................................................................................................17 10 USB PARAMETERS.......................................................................................................................................19 10.1 USB DC PARAMETERS.........................................................................................................................19 10.2 USB AC PARAMETERS.........................................................................................................................21 11 MECHANICAL OUTLINE ............................................................................................................................24 SMSC DS – USB97CFDC2-01 TABLE OF CONTENTS ....................................................................................................................11 Page 4 DATASHEET Rev. 02-27-07 ...
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... USB+ EXTERNAL FLASH ROM INTERFACE (26 Pins) FD0/OPT0 FD4/IN0 FA0 FA4 FA8 FA12 nFRD ROMEN XTAL1/CLKIN TST_OUT POWER, GROUNDS, and NO CONNECTS (46 Pins) SMSC DS – USB97CFDC2-01 FLOPPY DISK INTERFACE (14 Pins) nINDEX nWRTPRT DRVDEN0 DRVDEN1 nWGATE nHDSEL nMTR0 USB INTERFACE (4 Pins) USB- AVDD FD1/OPT1 ...
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... N.C. N.C. N.C. N.C. USB97CFDC2-01 N.C. GND N.C. N.C. N.C. N.C. VDD N.C. N.C. N.C. N.C. N.C. N.C. N.C. 1 SMSC DS – USB97CFDC2-01 USB97CFDC2 Page 6 DATASHEET 51 FA15 FA12 FA7 FA6 FA5 FA4 FA3 GND FA2 FA1 FA0 VDD FD0/OPT0 FD1/OPT1 FD2/OPT2 FD3/OPT3 ...
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... Control nFDPWR DRIVE INTERFACE nTRK0, nINDEX, nWRTPRT, nDSKCHG nRDATA, DRVDEN0, DRVDEN1, nWDATA, nWGATE, nHDSEL, nDIR, nMTR0, nDS0, nSTEP SMSC DS – USB97CFDC2-01 To USB Bus High Speed USB Serial Interface Engine XCVR CONTROL CLOCK SIE DMA RX/TX Queue 8051 CPU IRQ0 ...
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... Index nINDEX 74 Write Protect nWRTPRT 64 Motor On 0 nMTR0 65 Drive Select 0 nDS0 SMSC DS – USB97CFDC2-01 BUFFER TYPE SYMBOL FLOPPY DISK INTERFACE IS Raw serial bit stream from the disk drive, low active. Each falling edge represents a flux transition of the encoded data. OD12 This active low high current driver provides the encoded data to the disk drive ...
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... OPT3 pin must be tied high thru a resistor and the OPT[2:0] pins tied low thru a resistor (See configuration description section). These pins are not driven while the USB97CFDC2- SUSPEND mode and internal ROM mode is active. They are driven while in SUSPEND in external ROM mode.. IO8 ...
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... OD24 This active low signal is intended to activate an external power switch, either in the drive or on the system board, to supply power to the floppy disk drive active whenever the USB97CFDC2-01 is not in SUSPEND mode. IS This active low signal is used by the system to reset the chip. The active low pulse should be at least 100ns wide ...
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... Buffer Type Descriptions Table 1 - USB97CFDC2-01 Buffer Type Descriptions BUFFER IO8 IO8P OD12 O24 OD24 ICLKx OCLKx I/O-U SMSC DS – USB97CFDC2-01 DESCRIPTION I Input IP Input with 30uA pull-up IS Input with Schmitt trigger O8 Output with 8mA drive Input/output with 8mA drive Input/output with 8mA drive and 30uA pull-up Open drain… ...
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... If the internal ROM is used, OPT3 must be tied high and OPT[2:0] must be tied low through a resistor. In this mode, an external serial EEPROM is used to store the OEM’s USB assigned VID, their PID, their Product String, and the options for the particular drive connected to the USB97CFDC2-01. The data in the EEPROM is organized as follows: Note: If the data is not of the specified length, then fill the length with zeros, following the data ...
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... To know more about the format of the Device Descriptor and the Strings please refer to the USB 1.1 Specifications. For information on the UFI Inquiry Data, please refer to the “USB Mass Storage Class UFI Command Specification”. SMSC DS – USB97CFDC2-01 drive from ...
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... TSTOUT pin monitored for toggle of state toggle occurs, either the pin under test is discontinuous, or the TSTOUT pin is not connected on the board Pin1 Pin2 SMSC DS – USB97CFDC2-01 Pin3 Page 14 DATASHEET Pin100 TSTOUT Rev ...
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... High Input Leakage O8 Type Buffer Low Output Level V High Output Level V Output Leakage I/O8(P) Type Buffer V Low Output Level High Output Level V Output Leakage IO8 IO8P SMSC DS – USB97CFDC2-01 = 0°C - 70° MIN TYP MAX V 0.8 ILI V 2.0 IHI 0.4 ILCK 2.2 ...
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... Supply Current Active Supply Current Standby I CSBU Note 1: Output leakage is measured with the current pins in high impedance. Note 2: See Appendix A for USB DC electrical characteristics. CAPACITANCE T PARAMETER Clock Input Capacitance Input Capacitance Output Capacitance SMSC DS – USB97CFDC2-01 MIN TYP MAX 0 -10 + ...
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... FA[14:0] Address setup time to nFRD asserted t2 nFRD pulse width t3 FD[7:0] Data setup time to nFRD de-asserted t4 FD[7:0] Data hold time from nFRD de-asserted t5 FA[14:0] Address hold time from nFRD de-asserted SMSC DS – USB97CFDC2- FIGURE 1 - INPUT CLOCK TIMING Table 2 – Input Clock Timing Parameters MIN 41.9/ 27.9 ...
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... Pulse Width t7 nRDATA Active Time Low t8 nWDATA Write Data Width Low *X specifies one MCLK period and Y specifies one WCLK period. MCLK = 16x Data Rate (at 500 Kbp/s MCLK = 8 MHz) WCLK = 2x Data Rate (at 500 Kbp/s WCLK = 1 MHz) SMSC DS – USB97CFDC2- MIN TYP ...
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... Input Levels Differential Input Sensitivity Differential Common Mode Range Single Ended Receiver Threshold Output Levels Static Output Low Static Output High Capacitance SMSC DS – USB97CFDC2-01 Common Mode Input Voltage (volts) Table Electrical Characteristics CONDITIONS SYMBOL (NOTE 1, 2) MIN VBUS 4.4 ICC ...
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... Note 2: All timing use a capacitive load (CL) to ground of 50pF, unless otherwise specified. Note 3: This is relative to VUSBIN. Note 4: This is dependent on block configuration set by software. Note 5: When the internal ring oscillator and waiting for first setup packet. SMSC DS – USB97CFDC2-01 CONDITIONS SYMBOL (NOTE 1, 2) ...
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... Full Speed 20ns at C FIGURE 5 - DATA SIGNAL RISE AND FALL TIME T PERIOD Differential Data Lines T PERIOD Crossover Differential Data Lines FIGURE 7 - DIFFERENTIAL TO EOP TRANSITION SKEW AND EOP WIDTH SMSC DS – USB97CFDC2-01 Rise Time 90% Differential Data Lines 10 50pF L Crossover Points Consecutive Transitions ...
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... To next Transition For Paired Transitions Source EOP Width Differential to EOP transition Skew Receiver Data Jitter Tolerance To next Transition For Paired Transitions EOP Width at receiver Must reject as EOP Must Accept TEOPR1 TEOPR2 SMSC DS – USB97CFDC2- Consecutive Transitions PERIOD JR1 Paired Transitions PERIOD ...
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... Note 4: Measured from 10% to 90% of the data signals. Note 5: The rising and falling edges should be smoothly transiting (monotonic). Note 6: Timing differences between the differential data signals. Note 7: Measured at crossover point of differential data signals. Note 8: These are relative to the 14.318 MHz crystal. SMSC DS – USB97CFDC2-01 CONDITIONS SYM (NOTE MIN (45 Ω ...
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... Note 2: Minimum space between protrusion and an adjacent lead is .007 mm. Note 3: Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm Note 5: Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC DS – USB97CFDC2-01 FIGURE 9 - 100 PIN TQFP PACKAGE MAX ~ 1 ...