ISP1161A1BD,118 STEricsson, ISP1161A1BD,118 Datasheet - Page 26

• Manufacturer Part Number: ISP1161A1BD,118
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,118

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

ISP1161A1_4
Product data sheet
Fig 24. ISP1161A1 HC USB transaction loop.
Initialize
Reset
Entry
HC
Description of
1. Reset: This includes hardware reset by pin RESET and software reset by the
2. Initialize HC: It includes:
3. Entry: The normal entry point. The microprocessor returns to this point when there
4. Need USB traffic: USB devices need the HC to generate USB traffic when they have
5. Prepare PTD data in microprocessor’s system RAM: The communication between
USBOperational
HC state =
HcSoftwareReset command (A9H). The reset function will clear all the HC’s internal
control registers to their reset status. After reset, the HCD must initialize the
ISP1161A1 USB HC by setting some registers.
a. Setting the physical size for the HC’s internal FIFO buffer RAM by setting the
b. Setting the HcHardwareConfiguration register according to requirements
c. Clearing interrupt events, if required
d. Enabling interrupt events, if required
e. Setting the HcFmInterval register (0DH to read, 8DH to write)
f. Setting the HC’s Root Hub registers
g. Setting the HcControl register to move the HC into USBOperational state
See also
are HC requests.
USB traffic requests such as:
a. Connecting to or disconnecting from the downstream ports
b. Issuing the Resume signal to the HC
To generate USB traffic, the HCD must enter the USB transaction loop.
the HCD and the ISP1161A1 HC is in the form of Proprietary Transfer Descriptor
(PTD) data. The PTD data provides USB traffic information about the commands,
status, and USB data packets.
The physical storage media of PTD data for the HCD is the microprocessor’s system
RAM. For the ISP1161A1 HC, the storage media is the internal FIFO buffer RAM.
The HCD prepares PTD data in the microprocessor system RAM for transfer to the
ISP1161A1 HC internal FIFO buffer RAM.
HcITLBufferLength register (2AH to read, AAH to write) and the
HcATLBufferLength register (2BH to read, ABH to write)
Section
HC informs HCD of
Figure
USB traffic results
USB traffic?
Need
Exit
24:
9.5.
Rev. 04 — 29 January 2009
no
yes
HC performs USB transactions
Prepare PTD data in
P system RAM
via USB bus I/F
USB single-chip host and device controller
Transfer PTD data into
HC FIFO buffer RAM
HC interprets
PTD data
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
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