ISP1583BS STEricsson, ISP1583BS Datasheet - Page 4

• Manufacturer Part Number: ISP1583BS
• Manufacturer: STEricsson

Specifications of ISP1583BS

• Lead Free Status / RoHS Status: Compliant

Fig 1.
RESET_N
1.5 kΩ
V
12 kΩ
CC(3V3)
(1) Pin 15 is shared by READY and IORDY.
(2) Pin 60 is shared by MODE0 and DA1.
(3) Pin 62 is shared by BUS_CONF and DA0.
3.3 V
RREF
The figure shows the ISP1583BS pinout. For the ISP1583ET, ISP1583ET1 and ISP1583ET2 ballouts, see
The direction of pins DREQ, DACK, DIOR and DIOW is determined by bit MASTER (DMA Hardware register) and bit ATA_MODE (DMA Configuration register).
Block diagram
RPU
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13, 35, 59
61
2
6
7
DGND
REGULATORS
to or from USB
HI-SPEED USB
TRANSCEIVER
POWER-ON
VOLTAGE
DP
RESET
AGND
3
DM
4
1, 5
SoftConnect
VCC1V8
1.8 V
internal
reset
32, 56
analog
supply
digital
supply
V
BUS
55
SUSPEND WAKEUP
ST-ERICSSON
CONTROLLER
SIE/PIE
SYSTEM
64
XTAL1
12 MHz
58
XTAL2
63
57
MANAGEMENT
INTEGRATED
MEMORY
RAM (8 kB)
UNIT
I/O pad supply
V
ISP1583
CC(I/O)
26, 41, 54
CONTROLLER
REGISTERS
OTG SRP
HANDLER
HANDLER
MODULE
MICRO-
DMA
DMA
CS0_N
CS1_N
21
22
DA0
MICROCONTROLLER
Table
DMA INTERFACE
62
DA1
(3)
INTERFACE
60
(2)
3.
DA2
17
DREQ
DACK
9
10 11 12
DIOR
DIOW
37 to 40,
004aaa268
42 to 53
23 to 25,
27 to 31
14
15
62
60
34
18
36
19
20
15
16
8
16
8
EOT
INTRQ
IORDY
DATA[15:0]
BUS_CONF
MODE0
MODE1
AD[7:0]
CS_N
ALE/A0
RW_N/RD_N
DS_N/WR_N
READY
INT
(1)
(2)
(1)
(3)