CS9211-VNG National Semiconductor, CS9211-VNG Datasheet - Page 17

• Manufacturer Part Number: CS9211-VNG
• Manufacturer: National Semiconductor

Specifications of CS9211-VNG

• Operating Temperature (max): 85C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Revision 2.1
Functional Description
3.2.1
Two commands are defined for the serial interface, a read
command and a write command. The read and write proto-
cols are summarized in Table 3-1. Figure 3-5 on page 18
shows the write cycle timing, and Figure 3-6 on page 18
shows the read cycle timing. In order for the CS9211 to
properly receive commands through the serial interface,
the DOTCLK input signal must be active.
The protocol begins with the assertion of the SCS input,
followed by activity on the SCLK (serial command clock)
and SDIN (serial data input) lines. The serial data must be
in the following order: one start bit (value = X), one control
bit (value = 1), 12 address bits, a read/write command bit
(1 = Write, 0 = Read), and 32 data bits. In the case of a
read, seven (7) idle clock pulses must occur between the
read command and the beginning of the 32 bits of data
transmission on the SDO line. After the last bit of the serial
data transfer, SCS should be deasserted.
The CS9211 samples the serial interface input signals on
the rising edge of SCLK. Therefore, data driven onto the
SDIN input should change on the falling edge of SCLK.
Data driven by the CS9211 onto the SDO output changes
on the rising edge of SCLK. Therefore data being read
should be sampled on the falling edge of SCLK.
3.2.1.1
1)
2)
Cycle(s)
Assert SCS input.
One SCLK period “don’t care” transfer (i.e., clock tog-
gle).
12
32
1
1
1
Serial Interface
Write Transfer Sequence (52 clocks)
1 Start bit
1 Control bit
12 Address bits
1 Write bit
32 data bits
Write Sequence with SCS = “1”
Table 3-1. Serial Interface Write/Read Sequences
(Continued)
ex: SDIN = A8A8_A8A8h
SDIN = Don’t care
SDIN = 1
SDIN = 4xx
SDIN = 1
17
Cycle(s)
3)
4)
5)
6)
7)
3.2.1.2
1)
2)
3)
4)
5)
6)
7)
8)
12
32
1
1
1
7
Write a 1 to SDIN.
Next, the address is transmitted with the LSB
(Address[0]) first... MSB (Address[11]) last.
The Write bit = 1.
The data is transmitted LSB (Data[0]) first... MSB
(Data[31]) last, on the positive edges of the next 32
SCLKS.
Deassert SCS (one clock period) and toggle SCLK for
four clock periods.
Assert SCS input.
One SCLK period “don’t care” transfer (i.e., clock tog-
gle).
Write a 1 to SDIN.
Next the address is transmitted with the LSB
(Address[0]) first ... MSB (Address[11]) last.
The Read bit = 0.
Seven SCLK periods of “don’t care” transfer (i.e., clock
toggles).
The data is transmitted on SDO with the LSB (Data[0])
first ... MSB (Data[31]) last, on the positive edges of
the next 32 SCLK .
Deassert SCS (one clock period) and toggle SCLK for
one clock period.
1 Control bit
12 Address bits
1 Read bit
7 Idle SCLKs
32 Read data bits
Read Transfer Sequence (56 clocks)
1 Start bit
Read Sequence with SCS = “1”
SDIN = 4xx
ex: SDIN = Don’t care
ex: SDO = A8A8_A8A8h
SDIN = Don’t care
SDIN = 1
SDIN = 0
www.national.com