CS9211-VNG National Semiconductor, CS9211-VNG Datasheet - Page 20

• Manufacturer Part Number: CS9211-VNG
• Manufacturer: National Semiconductor

Specifications of CS9211-VNG

• Operating Temperature (max): 85C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

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Functional Description
Offset 404h-407h
Offset 404h-407h
21:20
18:16
Bit
Bit
26
25
24
19
LP_HSYNC_SEL
COLOR_MONO
FLM_VSYNC_
DSTN_TFT
LDE_SEL
PIX_OUT
Name
Name
SEL
Table 3-3. Panel Interface Pin Function Selection Bits
Description
LP/HSYNC Select: Selects the function of LP/HSYNC (pin 31). Set this bit based on the panel type
connected. For DSTN or SSTN panels, set this bit to 0. For TFT panels, set this bit to 1.
0 = LP (output for DSTN/SSTN panel).
1 = HSYNC (output for TFT panel).
LDE Select: Always set this bit to 1.
0 = Reserved
1 = LDE (output for TFT panel).
FLM/VSYNC Select: Selects function of FLM/VSYNC (pin 33). Set this bit based on the panel type con-
nected. For DSTN or SSTN panels, set this bit to 0. For TFT panels, set this bit to 1.
0 = FLM (output for DSTN/SSTN panel).
1 = VSYNC (output for TFT panel).
Description
Panel Type Select: Selects panel type. The selection of the panel type in conjunction with the
PIX_OUT (bits [18:16]) setting determines how pixel data is mapped on the output LD/UD pins. This bit
also determines the generation of SHFCLK and other panel timing interface signals.
00 = SSTN/DSTN panel
01 = TFT panel
10 = Reserved
11 = Reserved
Color/Mono Select: Selects color or monochrome LCD panel. 0 = Color; 1 = Monochrome.
Pixel Output Format: These bits define the pixel output format. The selection of the pixel output format
in conjunction with the panel type selection (bits [21:20]) and the color/monochrome selection (bits
[19]) determines how the pixel data is formatted before being sent on to the LD/UD pins. These settings
also determine the SHFCLK period for the specific panel.
000 = 8-bit DSTN panel or up to 24-bit TFT panel with one pixel per clock.
001 = 16-bit DSTN panel or 18/24-bit TFT XGA panel with two pixels per clock.
010 = 24-bit DSTN panel
011 = 8-bit SSTN panel
100, 101, 110, and 111 = Reserved
(Continued)
Option 1: Mono 8-bit DSTN (bits [21:20] = 00 and bit 19 = 1)
Option 2: Color TFT with 1 pixel/clock (bits [21:20] = 01 and bit 19 = 0)
Option 1: Color 16-bit DSTN (bits [21:20] = 00 and bit 19 = 0)
Option 2: Mono 16-bit DSTN (bits [21:20] = 00 and bit 19 = 1)
Option 3: Color 18/24 bit TFT (bits [21:20] = 01 and bit 19 = 0)
Color 24-bit DSTN (bits [21:20] = 00 and bit 19 = 0)
Color 8-bit SSTN (bits [21:20] = 00 and bit 19 = 0)
Table 3-2. Panel Mode Selection Bits
Panel Timing Register 2 (R/W)
Panel Timing Register 2 (R/W)
(Color 8-bit DSTN is not supported)
SHFCLK = 1/4 of DOTCLK
SHFCLK = DOTCLK
SHFCLK = 1/(3:2:3) of DOTCLK
SHFCLK = 1/8 of DOTCLK
SHFCLK = 1/2 of DOTCLK
(Mono 24-bit DSTN is not supported)
SHFCLK = 1/4 of DOTCLK
SHFCLK = 1/(3:2:3) of DOTCLK
20
Reset Value = 00000000h
Reset Value = 00000000h
Revision 2.1