CS9211-VNG National Semiconductor, CS9211-VNG Datasheet - Page 25

• Manufacturer Part Number: CS9211-VNG
• Manufacturer: National Semiconductor

Specifications of CS9211-VNG

• Operating Temperature (max): 85C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Revision 2.1
Functional Description
Offset 404h-407h
Bit
4:0
30
29
27
26
23
22
13
HSYNC_TRAILING
LP_HSYNC_SEL
PSH_CLK_CTL
LDE_POL_SEL
VSYNC_POL
HSYNC_POL
PASS_THRU
CONT_LPS
_EDGE
Name
Table 3-8. Panel Output Timing Selection Bits (Continued)
Description
Horizontal Sync Trailing Edge Position: Selects the position of the trailing edge of the output
HSYNC pulse with respect to the rising edge of the modified input HSYNC pulse. The modified input
HSYNC pulse is that which has been inverted, or not inverted, by bit 29. The position is programma-
ble in steps of 1 DOTCLK, starting at 1 DOTCLOCK and extending up to 31. Bit 27 must be set in
order for bits [4:0] to be recognized. Note that there are combinations of bits [7:5] and [4:0] that can
result in a zero- or negative-length pulse, for example if the trailing edge is positioned before the
leading edge. In this case, the output pulse will not be generated.
00000 = Does not generate the HSYNC pulse if bit 27 = 0. (Default).
00001 - 11111 = The HSYNC trailing edge position can be varied from 1 to 31 DOTCLKs with
respect to the input HYSNC rising edge.
Pass-Through: Activates the Pass-Through mode. In Pass-Through mode, the input timing and the
pixel data are passed directly onto the panel interface timing and the panel data pins to drive the
panel; the internal CS9211 logic and timing is not used. In normal mode, Offset 400h[7:0], 404h[29],
and 404h[27:24] are effective.
0 = Normal mode; output timing uses the logic and timing from the CS9211.
1 = Pass-Through mode; CS9211 internal timing logic functions are not used.
Display Timing Strobe Polarity Select: Selects the polarity of the LDE pin (pin 32). This can be
used for some TFT panels that require an active low timing LDE.
0 = LDE signal is active low (Default).
1 = LDE signal is active high.
Panel Shift Clock Retrace Activity Control: Programs the shift clock (SHFCLK, pin 30) to be either
free running or active only during the display period. Some TFT panels recommend keeping the shift
clock running during the retrace time. This bit has no effect in DSTN or SSTN modes.
0 = Shift clock is active only during active display period.
1 = Shift clock is free running during the entire frame period.
LP/HSYNC Select: Selects the function of LP/HSYNC (pin 31). Set this bit based on the panel type
connected. For DSTN or SSTN panels, set this bit to 0. For TFT panels, set this bit to 1.
0 = LP (output for DSTN/SSTN panel).
1 = HSYNC (output for TFT panel).
Vertical Sync Output Polarity: Selects polarity of the output VSYNC signal (pin 33). This bit is
effective only for TFT panels; for this bit to function, bit 24 must be set to 1. Note that Offset 400h[30]
selects the polarity of the input HSYNC, whereas bit 23 selects the polarity of the output VSYNC.
0 = VSYNC output is active high.
1 = VSYNC output is active low.
Horizontal Sync Output Polarity: Selects polarity of output HSYNC signal (pin 31). This bit is effec-
tive only for TFT panels; for this bit to function, bit 26 must be set to 1. Note that Offset 400h[29]
selects the polarity of the input VSYNC, whereas bit 22 selects the polarity of the output HSYNC.
0 = HSYNC output is active high.
1 = HSYNC output is active low.
Continuous Line Pulses: This bit selects whether line pulses are continuously output or are output
only during the active display time. In most cases, DSTN panels require continuous line pulses
(LPs). This bit will have no effect if the CS9211 is set to TFT mode.
0 = Continuous line pulses.
1 = Line pulses during the display time only.
(Continued)
Panel Timing Register 2 (R/W)
25
Reset Value = 00000000h
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