ISP1160BD-T NXP Semiconductors, ISP1160BD-T Datasheet - Page 6
ISP1160BD-T
Manufacturer Part Number
ISP1160BD-T
Description
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1160BD-T.pdf
(87 pages)
Specifications of ISP1160BD-T
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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ISP1160-01_7
Product data sheet
Table 2.
Symbol
TEST_HIGH
INT
n.c.
n.c.
RESET_N
NDP_SEL
EOT
DGND
n.c.
TEST_LOW
n.c.
TEST_LOW
H_WAKEUP
n.c.
H_SUSPEND
XTAL1
XTAL2
DGND
H_PSW1_N
H_PSW2_N
n.c.
n.c.
H_DM1
[1]
Pin description LQFP64
Pin
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Rev. 07 — 29 September 2009
Type
-
O
-
O
I
I
I
-
-
-
-
-
I
-
O
I
O
-
O
O
-
-
AI/O
Description
this pin must be connected to V
resistor
HC interrupt output; programmable level, edge triggered and
polarity; see
no connection; leave this pin open
no connection; leave this pin open
reset input (Schmitt trigger); a LOW level produces an
asynchronous reset (internal pull-up resistor)
indicates to the HC software the Number of Downstream Ports
(NDP) present:
0 — select 1 downstream port
1 — select 2 downstream ports
only changes the value of the NDP field in the
HcRhDescriptorA register; both ports will always be enabled;
see
(internal pull-up resistor)
DMA master device to inform the ISP1160/01 of end of DMA
transfer; active level is programmable; when not in use, this
pin must be connected to V
see
digital ground
no connection; leave this pin open
this pin must be connected to DGND via an external 10 kΩ
resistor
no connection; leave this pin open
this pin must be connected to DGND via a 1 MΩ resistor
HC wake-up input; generates a remote wake-up from the
suspend state (active HIGH); when not in use, this pin must be
connected to DGND via an external 10 kΩ resistor (internal
pull-down resistor)
no connection; leave this pin open
HC suspend state indicator output; active HIGH
crystal input; connected directly to a 6 MHz crystal; when this
pin is connected to an external clock source, pin XTAL2 must
be left open
crystal output; connected directly to a 6 MHz crystal; when
pin XTAL1 is connected to an external clock source, this pin
must be left open
digital ground
power switching control output for downstream port 1;
open-drain output
power switching control output for downstream port 2;
open-drain output
no connection; leave this pin open
no connection; leave this pin open
USB D− data line for HC downstream port 1
…continued
Section 10.3.1
Section 10.4.1
Section 10.4.1
Embedded USB host controller
CC
via an external 10 kΩ resistor;
CC
via an external 10 kΩ
ISP1160/01
© ST-ERICSSON 2009. All rights reserved.
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