MC10XS3412CPNA Freescale, MC10XS3412CPNA Datasheet

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... V DD MCU GND Figure 1. 10XS3412 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2008. All rights reserved. MOSFETs (dual DS(ON) MC10XS3412CPNA MC10XS3412DPNA PWR DD 10XS3412 VDD ...

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... Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics. ...

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... DWN PWM Module Calibratable Oscillator V REG Programmable FSI Watchdog Over-temperature Prewarning Figure 2. 10XS3412 Simplified Internal Block Diagram Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM Internal Over/Under-voltage POR Regulator Protections V REG Selectable Over-current Detection Severe Short-circuit Logic Detection Over-temperature ...

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... This pin is a command data input pin connected to the SPI serial data output Serial Input of the MCU or to the SO pin of the previous device of a daisy This pin is an external voltage input pin used to supply power interfaces to the SPI bus FSI 23 GND 22 HS2 21 HS0 Definition - chain of devices. Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... NC N/A 24 FSI Input Analog Integrated Circuit Device Data Freescale Semiconductor Formal Name These pins, internally shorted, are the ground for the logic and analog circuitry Ground of the device. These ground pins must be also shorted in the board. power for the device. This output pin is connected to the SPI serial data input pin of the MCU or to ...

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... HS[0:3] 100 CL [0:3] V ± 8000 ESD1 V ± 2000 ESD2 V ± 750 ESD3 V ± 500 ESD4 125 150 150 STG ° = 150 C initial 1500 Ω), the Machine Model (MM) = 100 pF, R ZAP = 4.0 pF). Analog Integrated Circuit Device Data Freescale Semiconductor Unit ° C ° C ...

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... Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics. ...

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... V mA – 1.6 2.2 – 5.0 – μA – – 5 0.2 0.8 1.5 V 3.3 3.9 4.3 V 0.5 - 0.9 V PWR(UV) 3.4 4.1 4.5 V 2.2 2.5 2.8 V voltage is restored to normal as long as the PWR Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Maximum Severe Short-Circuit Impedance Detection Notes 14. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity V 15. Short-circuit impedance calculated from HS[0:3] to GND pins. Value guaranteed per design. Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 3.0 V ≤ V ≤ 5 40°C ≤ T PWR DD Symbol ( ° ...

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... Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... A 1 Current Recopy Accuracy with one calibration point (6.0 V < V SR0 (17 Output Current 5.0 A Notes 17. Based on statistical analysis not production tested. Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 3.0 V ≤ V ≤ 5 40°C ≤ T PWR DD Symbol < SR0_1_ACC < C HS[0:3] ...

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... V +0. – 100 2.0 3.0 4.0 100 300 600 2.5 5 -1.2 V -0.8 V -0.4 PWR PWR PWR - 22 – -16 155 175 195 measured I at room CSNS 2 CSNS OLD(THRES) Analog Integrated Circuit Device Data Freescale Semiconductor Unit ° μ ° ...

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... The current must be limited by a series resistance when using voltages > 7.0 V. 23. Pull-down current is with V > 1.0 V and V SI 24. Pull-up current is with V < 2 25. In Fail-safe HS[0:3] depends respectively on ON[0:3]. FSI has an active internal pull- Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 3.0 V ≤ V ≤ 5 40°C ≤ T PWR DD Symbol DWN I ...

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... V/μs 0.3 0.6 1.2 V/μs 0.15 0.3 0.6 V/μs 0.07 0.15 0.3 V/μs 0.3 0.6 1.2 μ μs 0.8 1.0 1.2 μs -25 -5.0 15 Figure 4, page 21 with HS PWR ) that would turn the output OFF CS Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Time necessary for CSNS to be within ±5% of the targeted value (from HS voltage = 50 31. For FSI open, the Watchdog timeout delay measured from the rising edge of RST, to HS[0,2] output state depend on the corresponding input command. Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 3.0 V ≤ V ≤ 5 40°C ≤ T PWR DD ...

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... Freescale Semiconductor ...

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... Output Over-current Time Step for 28 W bit = 1 OC[1:0]=00 (slow by default) OC[1:0]=01 (fast) OC[1:0]=10 (medium) OC[1:0]=11 (very slow) Analog Integrated Circuit Device Data Freescale Semiconductor DYNAMIC ELECTRICAL CHARACTERISTICS ≤ 3.0 V ≤ V ≤ 5 40°C ≤ T PWR DD = 25°C under nominal conditions, unless ...

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... Freescale Semiconductor ...

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... For values outside this range, a calibration is needed between the PWM duty-cycle programming and the PWM on the output with R = 5.0 Ω resistive load. L 34. Typical value guaranteed per design. 35. Value guaranteed per statistical analysis. Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 3.0 V ≤ V ≤ 5 40°C ≤ T PWR DD Symbol f IN0 (32) ...

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... Analog Integrated Circuit Device Data Freescale Semiconductor Unit MHz μs μs μ ...

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... I OC1 Load I OC2 Current I OC3 I OC4 I OCLO4 I OCLO3 I OCLO2 I OCLO1 t OC1 Analog Integrated Circuit Device Data Freescale Semiconductor TIMING DIAGRAMS DLY(ON) DLY(OFF Figure 4. Output Slew Rate and Time Delays t t OC3 t t OC5 OC6 OC4 t OC2 Figure 5. Over-current Shutdown Protection ELECTRICAL CHARACTERISTICS ...

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... Don’t Care Valid 10% V 0.2VDD DD Previous OFF duration (toff TCSB CS 90% V 0.7VDD DD t Tlag LAG t TfSI FSI Don’t Care Valid Analog Integrated Circuit Device Data Freescale Semiconductor VIH V IH VIL V IL VIH V IH VIL VIH IH VIL V IL VIH VIL ...

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... SCLK SO 0.2 VDD SO 10% V Low-to-High Low to High SO SO 90% V 0.7 VDD High to Low High-to-Low Figure 8. SCLK Waveform and Valid SO Data Delay Time Analog Integrated Circuit Device Data Freescale Semiconductor t t RSI FSI TrSI TfSI DD 50% t SO(EN) TdlyLH 90% V 0.7 VDD DD DD ...

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... SPI circuit. In the event V the device goes to Fail-safe Mode The device transfers status . The SO output driver is enabled when has an active internal logic [1], signals at the SCLK and SI CS Table 10, page 35. Register Table 11, . DWN is lost (V Failure Analog Integrated Circuit Device Data Freescale Semiconductor CS CS ...

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... SCLK and reads out on the falling edge of SCLK. SO reporting descriptions are provided in page 40. Analog Integrated Circuit Device Data Freescale Semiconductor HIGH SIDE OUTPUTS (HS3, HS1, HS0, HS2) Protected 10 mΩ and 12 mΩ high side power outputs to the load. ...

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... In Fail-safe Mode, each lamp is controlled with dedicated parallel input pins. The device is configured in default mode. Self-protected High Side Switches HS0 - HS3 Self-protected High Side Switches Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... DO, D1, D2, ... , and D15 relate to the most recent ordered entry of program data into the LUX IC Figure 9. Single 16-Bit Word SPI Communication Analog Integrated Circuit Device Data Freescale Semiconductor The pins of the 10XS3412 follow a first-in first-out (D15 to D0) protocol, with both input and output words transferring the most significant bit (MSB) first ...

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... FSI is open Device is currently in Fault Mode. The faulted output(s) is (are) OFF. The safe autoretry circuitry is active to turn-on again the output(s). (fail=0) and (wake-up=1) and (fault=0) (wake-up=0) and Normal and Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... PWM ((n+1)/128 duty cycle 1111111 Analog Integrated Circuit Device Data Freescale Semiconductor The timing includes seven programmable PWM switching delay (number of PWM clock rising edges) to improve overall EMC behavior of the light module Table 8. Output PWM Switching Delay Delay bits and ...

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... PWM clock on IN0 input pin after maximum 200 μs (min. 50 μs). If the correct start-up sequence is not provided, the PWM function is not guaranteed. are within the normal voltage range DD pin to logic [0] for RST input is pulled up: pin. FS Table 11 and Table Analog Integrated Circuit Device Data Freescale Semiconductor 23). ...

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... PWM Analog Integrated Circuit Device Data Freescale Semiconductor In steady state, the wire harness will be protected by OCLO2 current level by default. Three other DC over-current levels are available: OCLO1 or OCLO3 or OCLO4 based on the state of the OCLO[1,0] bits. If the load current level ever reaches the over-current detection level, the corresponding output will latch the output OFF and FS will be also latched to logic [0] ...

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... V DD value. < the outputs will turn off, PWR PWR(UV) condition VDD = 0. Any new OT fault is . The output state is not changed as long as (UV) with V in nominal voltage range, DD(FAIL) PWR supplies is below V voltage PWR SUPPLY(POR) Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Output Shorted to VPWR Fault The 10XS3412 incorporates output shorted to VPWR detection circuitry in OFF state. Output shorted to VPWR fault is detected if output voltage is higher than reported as a fault condition when the output is disabled Analog Integrated Circuit Device Data Freescale Semiconductor (fault_control=0) (OpenloadON=1) (SC= hson=1 ...

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... SPI register contents are reset with default SUPPLY(POR) values corresponding to all SPI bits are set to logic [0] and all latched faults are also reset. EMC PERFORMANCES All following tests are performed on Freescale evaluation board in accordance with the typical application schematic. Analog Integrated Circuit Device Data resistor Ω ...

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... D10 D9 LSB D8:D0 Analog Integrated Circuit Device Data Freescale Semiconductor The 10XS3412 successfully meets the Class 5 of the CISPR25 emission standard and 200 V/m or BCI 200 mA injection level for immunity tests. LOGIC COMMANDS AND REGISTERS remaining nine bits D0, are used to configure and control the outputs and their protection features ...

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... SOA0 PWM3_s PWM2_s PWM1_s PWM0_s SR0_s DELAY2_s DELAY1_s DELAY0_s OLLED_en CSNS_ratio OCHI_s OCLO1_s OCLO0_s OC_mode_ CSNS1 CSNS0 X OV_dis (D13) HS Selection 0 0 HS0 (default) 1 HS1 0 HS2 1 HS3 7, page 29. A 010— OUTPUT CONFIGURATION 1 0 (Table 12). Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... VPWR protection for the selected output, the default value [0] corresponds to enable this feature. Analog Integrated Circuit Device Data Freescale Semiconductor A logic [1] on bit D3 (OLON_dis_s) disables the ON output open-load detection for the selected output, the default value [0] corresponds to enable this feature ...

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... OC0_s (D4) Profile Curves Speed 0 slow (default) 1 fast 0 medium 1 very slow , as shown Figure 14. OC1 Time OC3 t OC5 OC7 OC6 OC4 Table 18. Steady State Current 0 OCLO2 (default) 1 OCLO3 0 OCLO4 1 OCLO1 Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... HS0 (default Analog Integrated Circuit Device Data Freescale Semiconductor Table 22. Output Current Recopy Selection 1 The GCR register disables the over-voltage protection (D0). When this bits is [0], the over-voltage is enabled (default value). ADDRESS 00111 — CALIBRATION REGISTER (CALR) The CALR register allows the MCU to calibrate internal ...

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... PWM2_s PWM1_s SR1_s SR0_s DELAY2_s DELAY1_s OS_dis_ OLON_dis_s OLOFF_dis_s OLLED_en_ s s OC0_s OCHI_s OCLO1_s OCLO0_s CSNS_e CSNS1 CSNS0 CLOCK_fail X CAL_fail IN2 IN1 IN3 IN0 001 Analog Integrated Circuit Device Data Freescale Semiconductor 23. OD0 OC_s PWM0_s DELAY0_s CSNS_ratio_ s OC_mode_s OV_dis OTW WD_en 0 0 ...

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... OTWAR PREVIOUS ADDRESS SOA4 : SOA0 = 01111 (DIAGR1) The returned data OD4: OD1 report in real time the state of the direct input IN[3:0]. Analog Integrated Circuit Device Data Freescale Semiconductor A 010 The OD0 indicates if the watchdog is enabled (set to logic 1 0 [1]) or not (set to logic [0]). OD4:OD1 report the output state ...

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... SCLK CS RST SI SO CSNS FSI 4.7k 10k 10k 10k 10k Watchdog direct light commands (pedal, comodo,...) V PWR VPWR 100nF 100nF HS0 22nF LOAD 0 HS1 22nF LOAD 1 HS2 22nF LOAD 2 HS3 22nF GND LOAD 3 Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... J-STD-020C Sn-Pb reflow profile. The maximum peak temperature during the soldering process should not exceed 245 for 10 seconds maximum duration. Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING SOLDERING INFORMATION The DPNA code was qualified in accordance with JEDEC standards J-STD-020C Pb-free reflow profile. The maximum peak temperature during the soldering process should not exceed 260 for 40 seconds maximum duration ...

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... PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the 98ARL10596D listed below. 10XS3412 44 PACKAGE DIMENSIONS PNA SUFFIX 24-PIN PQFN NONLEADED PACKAGE 98ARL10596D ISSUE D Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Analog Integrated Circuit Device Data Freescale Semiconductor PNA SUFFIX 24-PIN PQFN NONLEADED PACKAGE 98ARL10596D ISSUE D PACKAGING PACKAGE DIMENSIONS 10XS3412 45 ...

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... PACKAGING PACKAGE DIMENSIONS 10XS3412 46 PNA SUFFIX 24-PIN PQFN NONLEADED PACKAGE 98ARL10596D ISSUE D Figure 15. Package Mechanical Outline Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Package Mechanical Outline Analog Integrated Circuit Device Data Freescale Semiconductor PNA SUFFIX 24-PIN PQFN NONLEADED PACKAGE 98ARL10596D ISSUE D PACKAGING PACKAGE DIMENSIONS 10XS3412 47 ...

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... Figure 16. Detail of Copper Traces Under Device with 10XS3412PNA 24-PIN PQFN PNA SUFFIX (PB-FREE) 98ARL10596D 24-PIN PQFN (12 x 12) Note For package dimensions, refer to the 10XS3412 data sheet. 0.2mm 0.2mm 0.5mm dia. Thermal Vias Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Figure 17. 1s JEDEC Thermal Test Board Layout Transparent Top View MC10XS3412 Pin Connections 24-PIN PQFN (12 x 12) 0.9 mm Pitch 12.0mm 12.0mm Body Analog Integrated Circuit Device Data Freescale Semiconductor Figure 18. 2s2p JDEC Thermal Test Board (Red - Top Layer, Yellow - Two Buried Layers ...

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... Heat spreading area [sqmm] RJA11 RJA12=RJA21 1 = Power Chip Logic Chip Area ( 46.42 37.03 150 41.60 32.90 300 40.02 31.63 450 38.86 30.68 600 38.04 29.99 400 500 600 RJA22 Analog Integrated Circuit Device Data Freescale Semiconductor (°C/ 53.82 51.27 55.05 49.47 48.63 ...

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... JEDEC Standard Thermal Test Board with Heat Spreading Areas 600 Sq. mm 100 10 1 0.1 0.000001 Figure 22. Transient Thermal 1W Step Response; Device on 2s2p JEDEC Standard Thermal Test Board Analog Integrated Circuit Device Data Freescale Semiconductor 0.0001 0.01 1 Time[s] RJA11 RJA12 RJA22 0.0001 ...

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... Added MC10XS3412DPNA part number. The “D” version has different soldering limits. 9.0 • Corrected minor formatting 10/2009 10.0 • Separated definitions for the 10XS3412C and 10XS3412D in the Static and Dynamic Tables and created a Device Variation Table on page 2. 10XS3412 52 REVISION HISTORY Analog Integrated Circuit Device Data Freescale Semiconductor ...

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