CY8C5487LTI-007 Cypress Semiconductor Corp, CY8C5487LTI-007 Datasheet - Page 16

• Manufacturer Part Number: CY8C5487LTI-007
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5487LTI-007

• Lead Free Status / RoHS Status: Compliant

security is needed in your application. The PSoC device also
offers an advanced security feature called Device Security which
permanently disables all test, programming, and debug ports,
protecting your application from external access (see the
“Device Security”
how to take full advantage of the security features in PSoC, see
the PSoC 5 TRM.
Table 5-1. Flash Protection
Disclaimer
Note the following details of the flash code protection features on
Cypress devices.
Cypress products meet the specifications contained in their
particular Cypress data sheets. Cypress believes that its family
of products is one of the most secure families of its kind on the
market today, regardless of how they are used. There may be
methods, unknown to Cypress, that can breach the code
protection features. Any of these methods, to our knowledge,
would be dishonest and possibly illegal. Neither Cypress nor any
other semiconductor manufacturer can guarantee the security of
their code. Code protection does not mean that we are guaran-
teeing the product as “unbreakable.”
Document Number: 001-55036 Rev. *F
Unprotected
Factory
Upgrade
Field Upgrade Internal read and write
Full Protection Internal read
Protection
Setting
External read and write
+ internal read and write
External write + internal
read and write
section on page 56). For more information on
Allowed
-
External read
External read and
write
External read and
write + internal write
PRELIMINARY
Not Allowed
Cypress is willing to work with the customer who is concerned
about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously
improving the code protection features of our products.
5.4 EEPROM
PSoC EEPROM memory is a byte addressable nonvolatile
memory. The CY8C54 has 2 KB of EEPROM memory to store
user data. Reads from EEPROM are random access at the byte
level. Reads are done directly; writes are done by sending write
commands to an EEPROM programming interface. CPU code
execution can continue from flash during EEPROM writes.
EEPROM is erasable and writeable at the row level. The
EEPROM is divided into two sections, each containing 64 rows
of 16 bytes each.
The CPU can not execute out of EEPROM. There is no ECC
hardware associated with EEPROM. If ECC is required it must
be handled in firmware.
5.5 External Memory Interface
CY8C54 provides an External Memory Interface (EMIF) for
connecting to external memory devices. The connection allows
read and write accesses to external memories. The EMIF
operates in conjunction with UDBs, I/O ports, and other
hardware to generate external memory address and control
signals.
Figure 5-1
synchronous and asynchronous memories. The CY8C54 only
supports one type of external memory device at a time.
External memory is located in the Cortex-M3 external RAM
space; it can use up to 24 address bits. See
section on page 18. The memory can be 8 or 16 bits wide.
Cortex-M3 instructions can be fetched/executed from external
memory, although at a slower rate than from flash.
is the EMIF block diagram. The EMIF supports
PSoC
®
5: CY8C54 Family Data
“Memory Map”
Page 16 of 97
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