CY8C5487LTI-007 Cypress Semiconductor Corp, CY8C5487LTI-007 Datasheet - Page 6
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CY8C5487LTI-007
Manufacturer Part Number
CY8C5487LTI-007
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY8C5487LTI-007.pdf
(97 pages)
Specifications of CY8C5487LTI-007
Lead Free Status / RoHS Status
Compliant
- Current page: 6 of 97
- Download datasheet (3Mb)
Document Number: 001-55036 Rev. *F
Notes
2. Pins are No Connect (NC) on devices without USB. NC means that the pin has no electrical connection. The pin can be left floating or tied to a supply voltage or ground.
3. The center pad on the QFN package should be connected to digital ground (Vssd) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal.
(configurable XRES, GPIO) P1[2]
(TRACEDATA[2], GPIO) P2[6]
(TRACEDATA[3], GPIO) P2[7]
(TCK, SWDCK, GPIO) P1[1]
(TMS, SWDIO, GPIO) P1[0]
(TDO, SWV, GPIO) P1[3]
(I2C0: SDA, SIO) P12[5]
(I2C0: SCL, SIO) P12[4]
(nTRST, GPIO) P1[5]
(TDI, GPIO) P1[4]
Vboost
Vddio1
XRES
Vssb
Vssd
Vbat
Ind
PRELIMINARY
10
11
12
13
14
15
16
17
Figure 2-1. 68-Pin QFN Part Pinout
1
2
3
4
5
6
7
8
9
Lines show Vddio
to IO supply
association
(Top View)
QFN
PSoC
[3]
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
®
P0[3] (GPIO, OpAmp0-/Extref0)
P0[2] (GPIO, OpAmp0+)
P0[1] (GPIO, OpAmp0out)
P0[0] (GPIO, OpAmp2out)
P12[3] (SIO)
P12[2] (SIO)
Vssd
Vdda
Vssa
Vcca
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, 12C1: SCL)
P3[7] (GPIO, OpAmp3out)
P3[6] (GPIO, OpAmp1out)
Vddio3
5: CY8C54 Family Data
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