CY8C5487LTI-007 Cypress Semiconductor Corp, CY8C5487LTI-007 Datasheet - Page 40

• Manufacturer Part Number: CY8C5487LTI-007
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5487LTI-007

• Lead Free Status / RoHS Status: Compliant

7.2.3 Status and Control Module
The primary purpose of this circuitry is to coordinate CPU
firmware interaction with internal UDB operation.
Figure 7-10. Status and Control Registers
The bits of the control register, which may be written to by the
system bus, are used to drive into the routing matrix, and thus
provide firmware with the opportunity to control the state of UDB
processing. The status register is read-only and it allows internal
UDB state to be read out onto the system bus directly from
internal routing. This allows firmware to monitor the state of UDB
processing. Each bit of these registers has programmable
connections to the routing matrix and routing connections are
made depending on the requirements of the application.
7.2.3.15 Usage Examples
As an example of control input, a bit in the control register can
be allocated as a function enable bit. There are multiple ways to
enable a function. In one method the control bit output would be
routed to the clock control block in one or more UDBs and serve
as a clock enable for the selected UDB blocks. A status example
is a case where a PLD or datapath block generated a condition,
such as a “compare true” condition that is captured and latched
by the status register and then read (and cleared) by CPU
firmware.
7.2.3.16 Clock Generation
Each subcomponent block of a UDB including the two PLDs, the
datapath, and Status and Control, has a clock selection and
control block. This promotes a fine granularity with respect to
allocating clocking resources to UDB component blocks and
allows unused UDB resources to be used by other functions for
maximum system efficiency.
Document Number: 001-55036 Rev. *F
8-bit Status Register
(Read Only)
Routing Channel
System Bus
8-bit Control Register
(Write/Read)
PRELIMINARY
7.3 UDB Array Description
Figure 7-11
the array core, there are a DSI routing interfaces at the top and
bottom of the array. Other interfaces that are not explicitly shown
include the system interfaces for bus and clock distribution. The
UDB array includes multiple horizontal and vertical routing
channels each comprised of 96 wires. The wire connections to
UDBs, at horizontal/vertical intersection and at the DSI interface
are highly permutable providing efficient automatic routing in
PSoC Creator. Additionally the routing allows wire by wire
segmentation along the vertical and horizontal routing to further
increase routing flexibility and capability.
Figure 7-11. Digital System Interface Structure
7.3.1 UDB Array Programmable Resources
Figure 7-12
a bank of 16 UDBs. The primary programmable resources of the
UDB are two PLDs, one datapath and one status/control register.
These resources are allocated independently, because they
have independently selectable clocks, and therefore unused
blocks are allocated to other unrelated functions.
An example of this is the 8-bit Timer in the upper left corner of
the array. This function only requires one datapath in the UDB,
and therefore the PLD resources may be allocated to another
function. A function such as a Quadrature Decoder may require
more PLD logic than one UDB can supply and in this case can
utilize the unused PLD blocks in the 8-bit Timer UDB. Program-
mable resources in the UDB array are generally homogeneous
so functions can be mapped to arbitrary boundaries in the array.
UDB
UDB
UDB
UDB
shows an example of a 16 UDB array. In addition to
shows an example of how functions are mapped into
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System Connections
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5: CY8C54 Family Data
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