CY8C5386LTI-005 Cypress Semiconductor Corp, CY8C5386LTI-005 Datasheet - Page 23

• Manufacturer Part Number: CY8C5386LTI-005
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5386LTI-005

• Lead Free Status / RoHS Status: Compliant

6.2 Power System
The power system consists of separate analog, digital, and I/O supply pins, labeled Vdda, Vddd, and Vddiox, respectively. It also
includes two internal 1.8 V regulators that provide the digital (Vccd) and analog (Vcca) supplies for the internal core logic. The output
pins of the regulators (Vccd and Vcca) and the Vddio pins must have capacitors connected as shown in
pins must be shorted together, with as short a trace as possible, and connected to a 1 µF ±10% X5R capacitor. The power system
also contains a sleep regulator, an I
Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
shown in
6.2.1 Power Modes
PSoC 5 devices have four different power modes, as shown in
Table 6-2
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low power and portable devices.
PSoC 5 power modes, in order of decreasing power
consumption are:
Document Number: 001-55035 Rev. *F
Active
Alternate Active
Sleep
Figure
and
Table
2-4.
6-3. The power modes allow a design to
Vddio1
Vddio2
Vssd
0.1µF
2
C regulator, and a hibernate regulator.
0.1µF
I/ O Supply
I/O Supply
Domain
Digital
PRELIMINARY
Figure 6-4. PSoC Power System
1 µF
Regulators
Digital
0.1µF
Vddd
Vddd
Active is the main processing mode. Its functionality is config-
urable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and Real Time Clock
functionality. The lowest power mode is hibernate, which retains
register and SRAM state, but no clocks, and allows wakeup only
from I/O pins.
between power modes.
Hibernate
PSoC
0.1µF
I/ O Supply
Regulator
Regulator
Regulator
Regulator
Analog
Hibernate
Domain
Analog
Sleep
®
I2C
I/O Supply
5: CY8C53 Family Data Sheet
Figure 6-5
0.1µF
Vddio0
Vdda
Vcca
Vssa
Vddio3
illustrates the allowable transitions
Vddio0
1 µF
0.1µF
Vdda
Figure
0.1µF
.
6-4. The two Vccd
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