CY8C5386LTI-005 Cypress Semiconductor Corp, CY8C5386LTI-005 Datasheet - Page 41

• Manufacturer Part Number: CY8C5386LTI-005
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5386LTI-005

• Lead Free Status / RoHS Status: Compliant

Figure 7-12. Function Mapping Example in a Bank of UDBs
7.4 DSI Routing Interface Description
The DSI routing interface is a continuation of the horizontal and
vertical routing channels at the top and bottom of the UDB array
core. It provides general purpose programmable routing
between device peripherals, including UDBs, I/Os, analog
peripherals, interrupts, DMA and fixed function peripherals.
Figure 7-13
connect, which connects the UDB array routing matrix with other
device peripherals. Any digital core or fixed function peripheral
that needs programmable routing is connected to this interface.
Signals in this category include:
Document Number: 001-55035 Rev. *F
8-Bit
Timer
I2C Slave
Interrupt requests from all digital peripherals in the system.
DMA requests from all digital peripherals in the system.
Digital peripheral data signals that need flexible routing to I/Os.
Digital peripheral data signals that need connections to UDBs.
Connections to the interrupt and DMA controllers.
Connection to I/O pins.
Connection to analog system digital signals.
UART
UDB
UDB
UDB
UDB
Quadrature Decoder
illustrates the concept of the digital system inter-
HV
HV
A
B
8-Bit SPI
UDB
UDB
UDB
UDB
HV
HV
B
A
Logic
12-Bit PWM
12-Bit SPI
UDB
UDB
UDB
UDB
16-Bit
PWM
HV
HV
A
B
PRELIMINARY
16-Bit PYRS
8-Bit
Timer
UDB
UDB
UDB
UDB
Logic
HV
HV
B
A
Figure 7-13. Digital System Interconnect
Interrupt and DMA routing is very flexible in the CY8C53
programmable architecture. In addition to the numerous fixed
function peripherals that can generate interrupt requests, any
data signal in the UDB array routing can also be used to generate
a request. A single peripheral may generate multiple
independent interrupt requests simplifying system and firmware
design.
(Interrupt/DMA Multiplexer).
Figure 7-14. Interrupt and DMA Processing in the IDMUX
Fixed Function DRQs
Counters
Clocks
Global
PSoC
Timer
Fixed Function IRQs
Figure 7-14
Global
Clocks
CAN
®
5: CY8C53 Family Data Sheet
UDB Array
I2C
EMIF
Interrupt and DMA Processing in IDMUX
Digital System Routing I/F
Digital System Routing I/F
shows the structure of the IDMUX
IRQs
DRQs
UDB ARRAY
Controller
Interrupt
SAR
ADC
Detect
Detect
Edge
Edge
Blocks
Controller
SC
DMA
0
1
2
0
1
2
3
DACS
DMA termout (IRQs)
IO Port
Pins
Page 41 of 97
Comparators
Controller
Controller
Interrupt
DMA
IO Port
Pins
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