CY8C5386LTI-005 Cypress Semiconductor Corp, CY8C5386LTI-005 Datasheet - Page 95

• Manufacturer Part Number: CY8C5386LTI-005
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5386LTI-005

• Lead Free Status / RoHS Status: Compliant

Document Number: 001-55035 Rev. *F
Description Title: PSoC
Document Number: 001-55035
*C
2911720
®
5: CY8C53 Family Data Sheet Programmable System-on-Chip (PSoC
04/13/10
PRELIMINARY
MKEA
Updated Vb pin in PCB Schematic.
Updated Tstartup parameter in AC Specifications table.
Added Load regulation and Line regulation parameters to Inductive Boost
Regulator DC Specifications table.
Updated Icc parameter in LCD Direct Drive DC Specs table.
In page 1, updated internal oscillator range under Precision programmable
clocking to start from 3 MHz.
Updated Iout parameter in LCD Direct Drive DC Specs table.
Updated Table 6-2 and Table 6-3.
Added bullets on CapSense in page 1; added CapSense column in Section
12.
Removed some references to footnote [1].
Added footnote in PLL AC Specification table.
Added PLL intermediate frequency row with footnote in PLL AC Specs table.
Added UDBs subsection under 11.6 Digital Peripherals.
Updated Figure 2-6 (PCB Layout). Updated Pin Descriptions section and
modified Figures 6-6, 6-8, 6-9.
Updated LVD in Tables 6-2 and 6-3; modified Low power modes bullet in
page 1.
Added note to Figures 2-5 and 6-2; Updated Figure 6-2 to add capacitors for
Vdda and Vddd pins.
Updated boost converter section (6.2.2).
Updated Tstartup values in Table 11-3.
Removed IPOR rows from Table 11-68.
Updated 6.3.1.1, Power Voltage Level Monitors.
Updated section 5.2 and Table 11-2 to correct suggestion of execution from
flash.
Updated Vref specs in Table 11-21.
Updated IDAC uncompensated gain error in Table 11-25.
Added sentence to last paragraph of section 6.1.1.3.
Updated Tresp, high and low power modes, in Table 11-24.
Updated f_TCK values in Table 11-73 and f_SWDCK values in Table 11-74.
Updated SNR condition in Table 11-20.
Corrected unit of measurement in Table 11-21.
Updated sleep wakeup time in Table 6-3 and Tsleep in Table 11-3.
Added 1.71 V <= Vddd < 3.3 V, SWD over USBIO pins value to Table 11-74.
Removed mention of hibernate reset (HRES) from page 1 features, Table
6-3, Section 6.2.1.4, Section 6.3, and Section 6.3.1.1.
Changed PPOR/PRES to TBDs in Section 6.3.1.1, Section 6.4.1.6 (changed
PPOR to reset), Table 11-3 (changed PPOR to PRES), Table 11-68 (changed
title, values TBD), and Table 11-69 (changed PPOR_TR to PRES_TR).
Added sentence saying that LVD circuits can generate a reset to Section
6.3.1.1.
Changed Idd values on page 1, page 5, and Table 11-2.
Changed resume time value in Section 6.2.1.3.
Changed ESD HBM value in Table 11-1.
Removed Vdda = 1.65 V rows and changed BWag value in Table 11-22.
Changed Vioff values and changed CMRR value in Table 11-23.
Changed INL max value in Table 11-27.
Added max value to the Quiescent current specs in Tables 11-29 and 11-31.
Changed occurrences of “Block” to “Row” and deleted the “ECC not included”
footnote in Table 11-57.
Changed max response time value in Tables 11-69 and 11-71.
Changed the Startup time in Table 11-79.
Added condition to intermediate frequency row in Table 11-85.
Added row to Table 11-69.
Added brown out note to Section 11.8.1.
PSoC
®
5: CY8C53 Family Data Sheet
®
)
Page 95 of 97
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