STPCC5HEBIE STMicroelectronics, STPCC5HEBIE Datasheet - Page 82
STPCC5HEBIE
Manufacturer Part Number
STPCC5HEBIE
Description
Manufacturer
STMicroelectronics
Datasheet
1.STPCC5HEBIE.pdf
(93 pages)
Specifications of STPCC5HEBIE
Operating Temperature (min)
-40C
Operating Temperature (max)
115C
Applications
CapSense
Processing Unit
Microprocessor
Operating Supply Voltage (min)
2.45/3V
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
2.7/3.6V
Package Type
BGA
Screening Level
Industrial
Pin Count
388
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / RoHS Status
Compliant
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DESIGN GUIDELINES
6.4.4.3. Board Layout Issues
The physical layout of the motherboard PCB
assumed in this presentation is as shown in
6-24. For the PCI interface, the most critical signal
is the clock. Any skew between the clocks at the
PCI components and the STPC will impact the
timing budget. In order to get well matched clocks
at all components it is recommended that all the
PCI clocks are individually driven from a serial
resistance with matched routing lengths. In other
The
implementation. The exact timing constraints are
82/93
Note: The value of 22 Ohms corresponds to tracks with Z
Figure 6-25
HCLK
PCICLKO
PCICLKI
PCICLKx
describes a typical clock delay
PCICLKO
PCICLKI
Figure 6-24. Typical PCI clock routing
Figure 6-25. Clocks relationships
Release 1.5 - January 29, 2002
Figure
0
Length(PCICLKI) = Length(PCICLKx) with x = {A,B,C}
words, all clock line lengths that go from the
resistor to the PCI chips (PCICLKx) must be
identical.
The figure below is for PCI devices soldered on-
board. In the case of a PCI slot, the wire length
must be shortened by 2.5" to compensate the
clock layout on the PCI board. The maximum
clock skew between all devices is 2ns according
to PCI specifications.
listed in the PCI section of the Electrical
Specifications Chapter.
= 70 Ohms.
PCICLKA
PCICLKB
PCICLKC
Device A
Device B
Device C
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