STPCC4 STMicroelectronics, STPCC4 Datasheet

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X86 Core PC Compatible Information Appliance System-on-Chip POWERFUL x86 PROCESSOR 64-BIT SDRAM UMA CONTROLLER VGA & SVGA CRT CONTROLLER 135 MHz RAMDAC 2D GRAPHICS ENGINE VIDEO INPUT PORT VIDEO PIPELINE - UP-SCALER - VIDEO COLOUR SPACE CONVERTER - CHROMA & ...

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STPC CONSUMER-II X86 Processor core Fully static 32-bit five-stage pipeline, x86 processor fully PC compatible. Can access external memory. 8 Kbyte unified instruction and data cache with write back and write through capability. Parallel processing ...

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... The parts labeled STPCC5 are the upgraded parts and the differences are identified in both the Datash- eet and Programming Manual. All parts labeled STPCC4 do not support the new features outlined in the documentation. Where nor C4 nor C5 are specified, the information or feature applies to both versions. ...

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STPC CONSUMER-II 4/93 Release 1.5 - January 29, 2002 ...

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GENERAL DESCRIPTION At the heart of the STPC Consumer- advanced 64-bit x86 processor block. It includes a 64-bit SDRAM controller, advanced accelerated graphics and video controller, a high speed PCI local-bus controller and Industry standard PC chip ...

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GENERAL DESCRIPTION line flicker filter (primarily designed for Windows type displays). The fliker filter is optional and can be software disabled for use with large screen area’s of video. The Video output pipeline of the STPC Consumer- ...

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Peripheral activity detection. - Peripheral timer for detecting lack of peripheral activity - SUSP# modulation to adjust the system performance in various power down states of the system including full power on state. - Power control outputs to disable ...

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GENERAL DESCRIPTION Figure 1-1. Functional description. Host x86 I/F Core PCI m/s Local Bus I/F Video Pipeline - Pixel formating - Scaler - Colour Space CVT SVGA CRTC GE VIP SDRAM I/F 8/93 PMU ISA IPC PCI m/s 82C206 m/s ...

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CLOCK TREE The STPC Atlas integrates many features and generates all its clocks from a single 14MHz oscillator. This results in multiple clock domains as described in Figure 1-2. Figure 1-2. STPC Consumer-II clock architecture VCLK VIP CRTC,Video,TV DEVCLK ...

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GENERAL DESCRIPTION Figure 1-3. Typical ISA-based Application. Super I/O Flash ISA MUX IRQ MUX DMA.REQ STPC Consumer-II DMA.ACK DMUX PCI 10/93 Keyboard / Mouse Serial Ports Parallel Port Floppy RTC DMUX 4x 16-bit SDRAMs Release 1.5 - January 29, 2002 ...

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PIN DESCRIPTION 2.1. INTRODUCTION The STPC Consumer-II integrates most of the functionality of the PC architecture result, many of the traditional interconnections between the host PC microprocessor and the peripheral devices are totally internal to Consumer-II. This ...

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PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name Dir BASIC CLOCKS AND RESETS SYSRSETI# I SYSRSTO# O XTALI I XTALO I/O HCLK I/O DEV_CLK O DCLK I _xxx_PLL DD SDRAM CONTROLL ER MCLKI I MCLKO O ...

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Table 2-2. Definition of Signal Pins Signal Name Dir ISA INTERFACE ISA_CLK O ISA_CLK2X O OSC14M O LA[23:17] O SA[19:0] I/O SD[15:0] I/O ALE O MEMR#, MEMW# I/O SMEMR#, SMEMW# O IOR#, IOW# I/O MCS16#, IOCS16# I BHE# O ZWS# ...

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PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name Dir PCS3#,PCS1#,SCS3#,SCS1# O DIORDY O PIRQ, SIRQ I PDRQ, SDRQ I PDACK#, SDACK# O PDIOR#, SDIOR# O PDIOW#, SDIOW# O VGA CONTROLLER RED, GREEN, BLUE O VSYNC O HSYNC O ...

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Table 2-3. Buffer Type Descriptions Buffer Description ANA Analog pad buffer OSCI13B Oscillator, 13 MHz, HCMOS BT8TRP_TC Tri-State output buffer drive capability, Schmitt trigger with slew rate control and P, TC BD4STRP_FT LVTTL Bi-Directional drive capability, ...

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PIN DESCRIPTION 2.2. SIGNAL DESCRIPTIONS 2.2.1. BASIC CLOCKS AND RESETS SYSRSTI# System Reset/Power good. This input is low when the reset switch is depressed. Otherwise, it reflects the power supply power good signal. This input is asynchronous to all clocks, ...

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PCI_CLKO 33 MHz PCI Output Clock. This is the master PCI bus clock output. AD[31:0] PCI Address/Data. This is the 32-bit multiplexed address and data bus of the PCI. This bus is driven by the master during the address phase ...

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PIN DESCRIPTION master or an ISA master cycles by the STPC Consumer-II. ALE is driven low after reset. MEMR# Memory Read. This is the memory read command signal of the ISA bus used as an input when an ...

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ISACLK and ISACLKX2 as the input selection strobes. DACK_ENC[2:0] DMA Acknowledge. These are the ISA bus DMA acknowledge signals. They are encoded by the STPC Consumer-II before output and should be decoded externally using ISACLK and ISACLKX2 as the control ...

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PIN DESCRIPTION 2.2.7. VGA CONTROLLER RED, GREEN, BLUE RGB Video Outputs. These are the three analog colour outputs from the RAMDACs. These signals are sensitive to interference, therefore they need to be properly shielded. VSYNC Vertical Synchronisation Pulse. This is ...

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They can be used for the DDC1 (SCL) and DDC0 (SDA) lines of the VGA interface. SCAN_ENABLE Reserved . The pin is reserved for Test and Miscellaneous functions. COL_SEL Colour Select. Can be used for Picture in Picture function. Note ...

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PIN DESCRIPTION . Table 2-4. ISA / IDE Dynamic Multiplexing ISA BUS IDE (ISAOE (ISAOE RMRTCCS# DD[15] KBCS# DD[14] RTCRW# DD[13] RTCDS# DD[12] SA[19:8] DD[11:0] LA[23] SCS3# LA[22] SCS1# SA[21] PCS3# SA[20] PCS1# LA[19:17] DA[2:0] IOCHRDY ...

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Table 2-6. Signal value on Reset Signal Name PCI_GNT#[2:0] ISA BUS INTERFACE ISAOE# RMRTCCS# LA[23:17] SA[19:0] SD[15:0] BHE#, MEMR# MEMW#, SMEMR#, SMEMW#, IOR#, IOW# Unknown REF# ALE, AEN DACK_ENC[2:0] TC GPIOCS# RTCDS#, RTCRW#, KBCS# RTCAS LOCAL BUS INTERFACE PA[24:0] PD[15:0] ...

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PIN DESCRIPTION Table 2-7. Pinout. Pin # Pin name AF3 SYSRSETI# AE4 SYSRSETO# A3 XTALI C4 XTALO G23 HCLK H24 DEV_CLK AD11 DCLK AF15 MCLKI AB23 MCLKO AE16 MA[0] AD15 MA[1] AF16 MA[2] AE17 MA[3] AD16 MA[4] AF17 MA[5] AE18 ...

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Pin # Pin name D7 SERR# A6 LOCK# D20 PCI_REQ#[0] C21 PCI_REQ#[1] A21 PCI_REQ#[2] C22 PCI_GNT#[0] A22 PCI_GNT#[1] B21 PCI_GNT#[2] A5 PCI_INT#[0] C6 PCI_INT#[1] B4 PCI_INT#[2] D5 PCI_INT#[3] F2 LA[17]/DA[0[ G4 LA[18]/DA[1] F3 LA[19]/DA[2] F1 LA[20]/PCS1# G2 LA[21]/PCS3# G1 LA[22]/SCS1# ...

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PIN DESCRIPTION Pin # Pin name AC2 TDO AD12 VDDA_TV AF8 VDD_DAC1 1 G24 VDD_CPUCLK_PLL 1 AD13 VDD_DCLK_PLL 1 F25 VDD_DEVCLK_PLL 1 AC17 VDD_MCLKI_PLL 1 AC15 VDD_MCLKO_PLL 1 F26 VDD_HCLK_PLL 1 E25 VDD_SKEW_PLL 1 D11 VDD_CORE 1 L23 VDD_CORE 1 ...

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STRAP OPTIONS This chapter defines the STPC Consumer-II Strap Options and their location. Some strap options are left programmable for future versions of silicon. . Signal Designation MD1 Reserved MD2 HCLK PLL Speed MD3 MD4 PCICLKO Division MD5 MCLK/HCLK ...

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... For the parts referenced STPCC5, this s Bus or ISA mode ISA Mode 1 = Local Bus Mode This strap is not readable in a register for the STPCC4 . PCICLK division: This bit reflects the value sampled on [MD4] and is used together with MD[17] to select the PCICLK frequency. MD4 MD17 ...

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ADPC STRAP REGISTER 1 CONFIGURATION Strap1 Rsv This register defaults to the values sampled on MD[13:10] pins after reset Bit Number Sampled Mnemonic Bits 7-6 Rsv Bits 5-2 MD[13:10] Bits 1-0 Rsv Access = 0022h/0023h 4 ...

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... Internal. DCLK pin is an output and is connected to the internal frequency synthesizer output. Note this bit is writeable as well as readable. Reserved Reserved For the parts referenced STPCC4, see section Section 3.1.1. bits 1:0. For the parts referenced STPCC5.This bit is reserved and not connected Reserved Release 1.5 - January 29, 2002 Regoffset = 04Ch ...

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CPC STRAP REGISTER 0 CONFIGURATION HCLK_Strap MD[3} MD[2] MD[26] This register defaults to the values sampled on MD pins after reset Bit Number Sampled Mnemonic Bits 7-3 MD[3:2] & MD[26:24] Bits 2-0 Rsv Table 3-1. HCLK ...

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STRAP OPTIONS 32/93 Release 1.5 - January 29, 2002 ...

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ELECTRICAL SPECIFICATIONS 4.1. INTRODUCTION The electrical specifications in this chapter are valid for the STPC Consumer-II. 4.2. ELECTRICAL CONNECTIONS 4.2.1. POWER/GROUND CONNECTIONS/ DECOUPLING Due to the high frequency of operation of the STPC Consumer-II necessary to install ...

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ELECTRICAL SPECIFICATIONS 4.4. DC CHARACTERISTICS Symbol Parameter V Operating Voltage DD V Operating Voltage CORE P Supply Power 3.0V < Supply Power 2.45V < V CORE Except XTALI V Input Low Voltage IL XTALI Except XTALI V ...

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Table 4-5. VGA RAMDAC Power Consumption DCLK (MHz) - 6.25 - 135 Table 4-6. 2.5V Power Consumptions (V HCLK CPUCLK MCLK (MHz) (MHz) (MHz (x1) 66 100 100 (x1) 100 66 133 (x2 133 (x2) 100 ...

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ELECTRICAL SPECIFICATIONS 4.5. AC CHARACTERISTICS This section lists the AC characteristics of the STPC interfaces including output delays, input setup requirements, input hold requirements and output float delays. These measurements are based on the measurement points identified in Figure 4-1 ...

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Figure 4-2. CLK Timing Measurement Points (MIN) V Ref V IL (MAX) CLK One Clock Cycle LEGEND Minimum Time Minimum Time Clock Fall Time ...

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ELECTRICAL SPECIFICATIONS 4.5.1. POWER ON SEQUENCE Figure 4-3 describes the power-on sequence of the STPC, also called cold reset. There is no dependency between the different power supplies and there is no constraint on their rising time. SYSRSTI ...

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RESET SEQUENCE Figure 4-4 describes the reset sequence of the STPC, also called warm reset. The constraints on the strap options and the bus activities are the same as for the cold reset. The SYSRSTI# pulse duration must be ...

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ELECTRICAL SPECIFICATIONS 4.5.3. SDRAM INTERFACE Figure 4-5, Table 4-10 lists the AC characteristics of the SDRAM interface. Figure 4-5. SDRAM Timing Diagram MCLKx T delay MCLKI STPC.output STPC.input T hold Table 4-10. SDRAM Bus AC Timing Name Parameter Tcycle MCLKI ...

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PCI INTERFACE Table 4-11 lists the AC characteristics of the PCI interface. Table 4-11. PCI Bus AC Timing Name Parameter HCLK to PCICLKO delay (MD[30:27] = 0000) HCLK to PCICLKI delay PCICLKO Cycle Time PCICLKO High Time PCICLKO Low ...

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ELECTRICAL SPECIFICATIONS 4.5.5 IPC INTERFACE Table 4-12 lists the AC characteristics of the IPC interface. ISACLK2X T dly ISACLK T setup IRQ_MUX[3:0] DREQ_MUX[1:0] Table 4-12. IPC Interface AC Timings Name Parameter T ISACLK2X to ISACLK delay dly ISACLK2X to DACK_ENC[2:0] ...

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ISA INTERFACE AC TIMING CHARACTERISTICS Table 4-7 and Table 4-13 list the AC characteris- tics of the ISA interface. Figure 4-7 ISA Cycle (ref Table 4- ALE AEN Valid AENx 3 LA [23:17 ] Valid Address SA ...

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ELECTRICAL SPECIFICATIONS Name Parameter 10d Memory access to 8-bit ISA Slave 10e SA[19:0] & SBHE valid before IOR#, IOW# asserted 11 ISACLK2X to IOW# valid 11a Memory access to 16-bit ISA Slave - 2BCLK 11b Memory access to 16-bit ISA ...

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Name Parameter 24 IOR#, IOW# asserted before SA[19:0] 24o I/O access to 16-bit ISA Slave Standard cycle 24r I/O access to 16-bit ISA Slave Standard cycle 25 MEMR#, MEMW# asserted before next ALE# asserted 25b Memory access to 16-bit ISA ...

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ELECTRICAL SPECIFICATIONS Name Parameter 41 SA[19:0] SBHE valid to IOCHRDY negated 41a Memory access to 16-bit ISA Slave 41b Memory access to 8-bit ISA Slave 41c I/O access to 16-bit ISA Slave 41d I/O access to 8-bit ISA Slave 42 ...

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Name Parameter 64e IOW# negated to write data invalid MEMW# negated to copy data float, 8-bit ISA Slave, odd Byte 64f by ISA Master IOW# negated to copy data float, 8-bit ISA Slave, odd Byte by 64g ISA Master Note: ...

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ELECTRICAL SPECIFICATIONS 4.5.7. LOCAL BUS INTERFACE Figure 4-3 to Figure 4-11 and Table 4-15 list the AC characteristics of the Local Bus interface. Figure 4-8. Synchronous Read Cycle HCLK PA[ ] bus T setup CSx# PRD#[1:0] PD[15:0] Figure 4-9. Asynchronous ...

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Figure 4-10. Synchronous Write Cycle HCLK PA[ ] bus T setup CSx# PWR#[1:0] PD[15:0] Figure 4-11. Asynchronous Write Cycle HCLK PA[ ] bus T setup CSx# PWR#[1:0] PD[15:0] PRDY Release 1.5 - January 29, 2002 ELECTRICAL SPECIFICATIONS T T active ...

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ELECTRICAL SPECIFICATIONS The Table 4-14 below refers to Vh, Va, Vs which are the register value for Setup time, Active Time Table 4-14. Local Bus cycle lenght Cycle T setup Memory (FCSx Peripheral (IOCSx ...

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VGA INTERFACE Table 4-16 lists the AC characteristics of the VGA interface. Table 4-16. Graphics Adapter (VGA) AC Timing Name Parameter DCLK (input) Cycle Time DCLK (input) High Time DCLK (input) Low Time DCLK (input) Rising Time DCLK (input) ...

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ELECTRICAL SPECIFICATIONS 4.5.9 VIDEO INPUT PORT Table 4-17 lists the AC characteristics of the VIP interface. Table 4-17. Video Input AC Timings Name Parameter VCLK Cycle Time VCLK High Time VCLK Low Time VCLK Rising Time VCLK Falling Time VIN[7:0] ...

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IDE INTERFACE Table 4-18 lists the AC characteristics of the IDE interface. Name Parameters DD[15:0] setup to PIOR#/SIOR# falling DD[15:0} hold to PIOR#/SIO R# falling 4.5.11 JTAG INTERFACE Figure 4-12 and Table 4-17 list the AC characteristics of the ...

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ELECTRICAL SPECIFICATIONS Tjset TMS setup time Tjhld TMS hold time Tjset TDI setup time Tjhld TDI hold time Tjout TCLK to TDO valid Tpset STPC pin setup time Tphld STPC pin hold time Tpout TCLK to STPC pin valid 54/93 ...

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INTENSIONNALY BLANK ELECTRICAL SPECIFICATIONS Release 1.5 - January 29, 2002 55/93 ...

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ELECTRICAL SPECIFICATIONS 56/93 Release 1.5 - January 29, 2002 ...

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MECHANICAL DATA 5.1. 388-PIN PACKAGE DIMENSION The pin numbering for the STPC 388-pin Plastic BGA package is shown in Figure 5-1. Figure 5-1. 388-Pin PBGA Package - Top View ...

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MECHANICAL DATA Figure 5-2. 388-pin PBGA Package - PCB Dimensions A1 Ball Pad Corner A Table 5-1. 388-pin PBGA Package - PCB Dimensions Symbols Min A 34.95 35.00 B 1.22 1.27 C 0.58 0.63 D 1.57 1.62 E 0.15 0.20 ...

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Figure 5-3. 388-pin PBGA Package - Dimensions C Solderball A Table 5-2. 388-pin PBGA Package - Dimensions mm Symbols Min Typ A 0.50 0.56 B 1.12 1.17 C 0.60 0.76 D 0.52 0.53 E 0.63 0.78 F 0.60 0.63 G ...

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MECHANICAL DATA 5.2. 388-PIN PACKAGE THERMAL DATA The 388-pin PBGA package has a Power Dissipation Capability of 4.5W. This increases to 6W when used with a Heatsink. Figure 5-4. 388-Pin PBGA structure Signal layers Figure 5-5. Thermal Dissipation Without Heatsink ...

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Figure 5-6. Thermal Dissipation With Heatsink Board Ambient Junction Rca Case 3 Rjc Board Junction 8.5 Rjb Board Ambient Rba Ambient Rja = 9.5 C/W Release 1.5 - January 29, 2002 MECHANICAL DATA Board dimensions 12.7 ...

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MECHANICAL DATA 5.3. SOLDERING RECOMMENDATIONS High quality, low defect soldering requires identifying the optimum temperature profile for reflowing the solder paste, therefore optimizing the process. The heating and cooling rise rates must be compatible with the solder paste and components. ...

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DESIGN GUIDELINES 6.1. TYPICAL APPLICATIONS The STPC Consumer-II is well suited for many applications. Some of the implementations are described below. SDRAM FLASH PCI MODEM IDE / PCI microphone AUDIO SCART 1 VIP STV2310 SCART 2 6.1.1. WEB BOX ...

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DESIGN GUIDELINES 6.2. STPC CONFIGURATION The STPC is a very flexible product thanks to decoupled clock domains and to strap options enabling a user-optimized configuration. As some trade off are often necessary important analysis of ...

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ARCHITECTURE RECOMMENDATIONS This section describes the implementations for the STPC interfaces. For more details, download the Schematics from the STPC web site. 6.3.1. POWER DECOUPLING An appropriate decoupling of the various STPC power pins is mandatory for optimum behaviour. ...

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DESIGN GUIDELINES 6.3.3. SDRAM The STPC provides all the signals for SDRAM control 128 MBytes of main memory are supported. All Banks must be 64 bits wide memory banks are available when using 16Mbit devices. ...

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Figure 6-5. One Memory Banks with 8 Chips (8-bit) MCLKI 10pF MCLKO CY2305 CS0# MA[12:0] BA[1:0] RAS0# CAS0# WE# DQM[7:0] DQM[7] MD[63:0] MD[63:56] Figure 6-6. Two Memory Banks with 8 Chips (8-bit) MCLKI 22pF MCLKO CY2305 0 H CS1# CS0# ...

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DESIGN GUIDELINES For other implementations like 32-bit SDRAM devices, refers to the SDRAM controller signal SDRAM Density 16 Mbit Internal Banks 2 Banks DIMM Pin Number ... MA[10:0] 123 - 126 - 39 - 122 BA0 (MA11) Address Mapping: 16 ...

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In the case of higher clock load it is recommended to use a zero-delay clock buffer as described in Figure 6-8. This approach is also recommended Figure 6-8. PCI clock routing with zero-delay clock buffer PCICLKI PLL PCICLKO CY2305 Implementation ...

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DESIGN GUIDELINES 6.3.5. LOCAL BUS The local bus has all the signals to connect flash devices or I/O devices with the minimum glue logic. Figure 6-9. Typical 16-bit boot flash implementation 22 PA[22:1] FCS0# PRD0# PRD1# PWR0# PWR1# 16 PD[15:0] ...

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IPC Most of the IPC signals are multiplexed: Interrupt inputs, DMA Request inputs, DMA Acknowledge outputs. The figure below describes a complete implementation of the IRQ[15:0] time-multiplexing. Figure 6-10. Typical IRQ multiplexing Timer 0 Keyboard Slave PIC COM2/COM4 COM1/COM3 ...

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DESIGN GUIDELINES The figure below describes implementation of the external glue logic for DMA Request time-multiplexing and DMA Acknowledge demultiplexing. Like for the interrupt lines, this Figure 6-11. Typical DMA multiplexing and demultiplexing ISA, Refresh ISA, PIO ISA, FDC ISA, ...

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IDE / ISA DYNAMIC DEMULTIPLEXING Some of the ISA bus signals are dynamically multiplexed to optimize the pin count.Figure 6-12 Figure 6-12. Typical IDE / ISA Demultiplexing STPC bus / DD[15:0] MASTER# ISAOE# LA[22] LA[23] LA[24] LA[25] 6.3.8. BASIC ...

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DESIGN GUIDELINES 6.3.9. VGA INTERFACE The STPC integrates a voltage reference and video buffers. The amount of external devices is then limited to the minimum as described in the Figure 6-14. All the resistors and capacitors have ...

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TV INTERFACE The STPC integrates a voltage reference and video DACs. The amount of external devices is then limited to video buffers as described in the Figure 6-15. The connection from IREFx and VREFx up to the 20 ohms ...

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DESIGN GUIDELINES 6.3.11. JTAG INTERFACE The STPC integrates a JTAG interface for scan- chain and on-board testing. The only external Figure 6-16. Typical JTAG implementation 3V3 TCLK TDO TMS TDI TRST STPC 76/93 device needed are the pull up resistors.Figure ...

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PLACE AND ROUTE RECOMMENDATIONS 6.4.1. GENERAL RECOMMENDATIONS Some STPC Interfaces run at high speed and need to be carefully routed or even shielded like: 1) Memory Interface 2) PCI bus 3) Graphics and video interfaces 4) 14 MHz oscillator ...

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DESIGN GUIDELINES 6.4.3. MEMORY INTERFACE 6.4.3.1. Introduction In order to achieve SDRAM memory interfaces which work at clock frequencies of 100 MHz and above, careful consideration has to be given to the timing of the interface with all the various ...

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In other words, all Low skew clock driver: MCLKO * No additional 75mm when SDRAM directly soldered ...

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DESIGN GUIDELINES The DIMM sockets should be populated starting with the furthest DIMM from the STPC device first (DIMM1). There are two types of DIMM devices; single-row and dual-row. The dual-row devices require two chip select signals to select between ...

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PCI INTERFACE 6.4.4.1. Introduction In order to achieve a PCI interface which work at clock frequencies up to 33MHz, consideration has to be given to the timing of the interface with all the various electrical and physical constraints taken ...

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DESIGN GUIDELINES 6.4.4.3. Board Layout Issues The physical layout of the motherboard PCB assumed in this presentation is as shown inFigure 6-24. For the PCI interface, the most critical signal is the clock. Any skew between the clocks at the ...

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THERMAL DISSIPATION 6.4.5.1. Power saving Thermal dissipation of the STPC depends mainly on supply voltage. When the system does not need to work at the upper voltage limit, it may therefore be beneficial to reduce the voltage to the ...

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DESIGN GUIDELINES When considering thermal dissipation, one of the most important parts of the layout is the connection between the ground balls and the ground layer. Figure 6-27. Recommended 1-wire Power/Ground Pad Layout Considering only the central matrix of 36 ...

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To avoid solder wicking over to the via pads during soldering important to have a solder mask of 4 mil around the pad (NSMD pad). This gives a diameter of 33 mil for a 25 mil ground pad. ...

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DESIGN GUIDELINES As the PCB acts as a heat sink, the layout of top and ground layers must be done with care to maximize the board surface dissipating the heat. The only limitation is the risk of losing routing channels. ...

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Figure 6-32. Recommend signal wiring (top & ground layers) with corresponding heat flow GND Release 1.5 - January 29, 2002 Power Power DESIGN GUIDELINES Internal row STPC balls External row 87/93 ...

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DESIGN GUIDELINES 6.5. DEBUG METHODOLOGY In order to bring a STPC-based board to life with the best efficiency recommended to follow the check-list described in this section. 6.5.1. POWER SUPPLIES In parallel with the assembly process ...

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RMRTCCS# cycle to inform the ISA controller of a 16-bit device. 6.5.3.3. POST code Once the 16 first bytes are fetched and decoded, the CPU core continue its execution depending on the content of these first data. Usually, it corresponds ...

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DESIGN GUIDELINES Check: Measure PCICLKO: - maximum is 33MHz by standard - check selected frequency 6 PCI clocks - it is generated from HCLK by a division (1/2, 1/3 or 1/4) Check PCICLKI equals PCICLKO Measure MCLKO: ...

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... ORDERING DATA 7.1. ORDERING CODES STMicroelectronics Prefix Product Family PC: PC Compatible Product ID C4: Consumer-II Core Speed E: 100 MHz H: 133 MHz Memory Interface Speed D: 90 MHz E: 100 MHz Package B: 388 Overmoulded BGA Temperature Range C: Commercial Case Temperature (Tcase + Industrial Case Temperature (Tcase +115 C ...

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... ORDERING DATA 7.2. AVAILABLE PART NUMBERS Core Frequency Part Number ( MHz ) STPCC4HEBC 133 STPCC4HEBI 133 STPCC5HEBC 133 STPCC5HEBI 133 7.3. CUSTOMER SERVICE More information is available STMicroelectronics Internet www.st.com/stpc 92/93 CPU Mode Interface ( Speed (MHz) X2 100 X2 100 X2 100 X2 100 on the site http:// Release 1.5 - January 29, 2002 ...

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... N o license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...