STPCC03 STMicroelectronics, STPCC03 Datasheet
STPCC03
Available stocks
Related parts for STPCC03
STPCC03 Summary of contents
Page 1
POWERFUL x86 PROCESSOR 64-BIT 66MHz SDRAM UMA CONTROLLER -SUPPORTS 16Mbit SDRAMs (4MX4, 2MX8, 1MX16). VGA & SVGA CRT CONTROLLER 2D GRAPHICS ENGINE VIDEO INPUT PORT VIDEO PIPELINE - UP-SCALER - VIDEO COLOR SPACE CONVERTER - CHROMA & COLOUR KEY SUPPORT ...
Page 2
STPC CONSUMER-S OVERVIEW X86 Processor core Fully static 32-bit 5-stage pipeline, x86 processor fully PC compatible. Can access up to 4GB of external memory. 8Kbyte unified instruction and data cache with write back and write through capability. Parallel processing integral ...
Page 3
PCI Controller Fully compliant with PCI 2.1 specification. Integrated PCI arbitration interface masters can connect directly. External PAL allows for greater than 3 masters. Translation of PCI cycles to ISA bus. Translation of ISA master initiated cycle ...
Page 4
GENERAL DESCRIPTION 1 GENERAL DESCRIPTION At the heart of the STPC Consumer ad- vanced 64-bit processor block, dubbed the 5ST86. The 5ST86 includes a 5th generation processor core along with a 64-bit SDRAM con- troller, advanced 64-bit accelerated ...
Page 5
DOS type text line flicker filter (primarily designed for Win- dows type displays). The flicker filter is optional and can be software disabled for ...
Page 6
GENERAL DESCRIPTION state. - Peripheral activity detection. - Peripheral timer for detecting lack of peripheral activity - SUSP# modulation to adjust the system perform- ance in various power down states of the system including full power on state. - Power ...
Page 7
Figure 1-1. .Functionnal description. Host x86 I/F Core PCI m/s Local Bus I/F Video Pipeline - Pixel formating - Scaler - Colour Space CVT SVGA CRTC GE VIP SDRAM I/F GENERAL DESCRIPTION PMU watchdog ISA IPC PCI m/s 82C206 m/s ...
Page 8
GENERAL DESCRIPTION Figure 1-2. Typical Application Super I/O Flash ISA MUX IRQ MUX DMA.REQ STPC Consumer-S DMA.ACK DMUX PCI 4x 16-bit SDRAMs 8/59 Keyboard / Mouse Serial Ports Parallel Port Floppy RTC DMUX Issue 1.1 - October 16, 2000 2x ...
Page 9
PIN DESCRIPTION 2.1 INTRODUCTION The STPC Consumer-S integrates most of the functionalities of the PC architecture result, many of the traditional interconnections between the host PC microprocessor and the peripheral devices are totally internal to the STPC ...
Page 10
PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name Dir BASIC CLOCKS AND RESETS 2 SYSRSTI SYSRSTO# O XTALI I XTALO I/O 2 HCLK I/O DEV_CLK O 2 DCLK I _xxx_PLL DD MEMORY INTERFACE MCLKI ...
Page 11
Table 2-2. Definition of Signal Pins Signal Name Dir SA[19:0] I/O 2 SD[15:0] I/O 2 ALE MEMR# , MEMW# I SMEMR# , SMEMW IOR# , IOW# I MCS16# , IOCS16# ...
Page 12
PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name Dir MONITOR INTERFACE RED, GREEN, BLUE O 2 VSYNC O 2 HSYNC O VREF_DAC I RSET I COMP I VIDEO INPUT 2 VCLK I 2 VIN[7:0] I ANALOG TV OUTPUT ...
Page 13
SIGNAL DESCRIPTIONS 2.2.1 BASIC CLOCKS AND RESETS SYSRSTI# System Reset/Power good. This input is low when the reset switch is depressed. Other- wise, it reflects the power supply’s power good signal. This input is asynchronous to all clocks, and ...
Page 14
PIN DESCRIPTION CBE#[3:0] Bus Commands/Byte Enables. These are the multiplexed command and byte enable signals of the PCI bus. During the address phase they define the command and during the data phase they carry the byte enable information. These pins ...
Page 15
ISA master cycles by the STPC Consum- er-S. ALE is driven low after reset. MEMR# Memory Read. This is the memory read command signal of the ISA bus used as an in- put when an ...
Page 16
PIN DESCRIPTION interrupt controller, so that it may be connected di- rectly to the IRQ pin of the RTC. DREQ_MUX[1:0] ISA Bus Multiplexed DMA Re- quest. These are the ISA bus DMA request sig- nals. They are to be encoded ...
Page 17
PDRQ Primary DMA Request. SDRQ Secondary DMA Request. DMA request from IDE channels. PDACK# Primary DMA Acknowledge. SDACK# Secondary DMA Acknowledge. DMA acknowledge to IDE channels. PDIOR#, PDIOW# Primary I/O Read & Write. SDIOR#, SDIOW# Secondary I/O Read & Write ...
Page 18
PIN DESCRIPTION 2.2.11 MISCELLANEOUS SPKRD Speaker Drive. This the output to the speaker and is AND of the counter 2 output with bit 1 of Port 61, and drives an external speaker driver. This output should be connected to 7407 ...
Page 19
Table 2-3. ISA / IDE dynamic multiplexing . ISA BUS IDE (ISAOE (ISAOE RMRTCCS# DD[15] KBCS# DD[14] RTCRW# DD[13] RTCDS# DD[12] SA[19:8] DD[11:0] LA[23] SCS3# LA[22] SCS1# SA[21] PCS3# SA[20] PCS1# LA[19:17] DA[2:0] IOCHRDY DIORDY Figure ...
Page 20
PIN DESCRIPTION Table 2-5. Pinout. Pin # Pin name AF3 SYSRSTI# AE4 SYSRSTO# A3 XTALI C4 XTALO G23 HCLK H24 DEV_CLK AD11 DCLK AF15 MCLKI AB23 MCLKO AE16 MA[0] AD15 MA[1] AF16 MA[2] AE17 MA[3] AD16 MA[4] AF17 MA[5] AE18 ...
Page 21
Pin # Pin name D7 SERR# A6 LOCK# D20 PCI_REQ#[0] C21 PCI_REQ#[1] A21 PCI_REQ#[2] C22 PCI_GNT#[0] A22 PCI_GNT#[1] B21 PCI_GNT#[2] A5 PCI_INT[0] C6 PCI_INT[1] B4 PCI_INT[2] D5 PCI_INT[3] F2 LA[17]/DA[0] G4 LA[18]/DA[1] F3 LA[19]/DA[2] F1 LA[20]/PCS1# G2 LA[21]/PCS3# G1 LA[22]/SCS1# ...
Page 22
PIN DESCRIPTION Pin # Pin name F25 VDD_DEVCLK_PLL AC17 VDD_MCLKI_PLL AC15 VDD_MCLKO_PLL F26 VDD_HCLK_PLL A16 VDD5 B11 VDD5 B9 VDD5 D18 VDD5 D6 VDD D11 VDD D16 VDD D21 VDD F4 VDD F23 VDD L4 VDD L23 VDD T4 VDD ...
Page 23
STRAP OPTIONS This chapter defines the STPC Consumer-S Strap Options and their location Memory Data Refer to Designation Lines MD0 - Reserved MD1 - Reserved MD2 - Reserved MD3 - Reserved MD4 - Reserved MD5 - Reserved MD6 - ...
Page 24
STRAP OPTIONS Memory Data Refer to Designation Lines MD36 - Reserved MD37 - Reserved MD38 - Reserved MD39 - Reserved MD40 CPU CPU Mode MD41 - Reserved MD42 - Reserved MD43 - Reserved MD44 Reserved - MD45 - Reserved MD46 ...
Page 25
HCLK Strap register Configuration Index 5Fh (HCLK_Strap) Bits 7-6 Reserved . Bits 5-3 These pins reflect thevalue sampled on MD[26:24] pins respectively and control the Host clock frequency synthesizer as follows: Bit 5 Bit 4 Bit 3 Description 0 ...
Page 26
ELECTRICAL SPECIFICATIONS 4 ELECTRICAL SPECIFICATIONS 4.1 Introduction The electrical specifications in this chapter are val- id for the STPC Consumer-S. 4.2 Electrical Connections 4.2.1 Power/Ground Connections/Decoupling Due to the high frequency of operation of the STPC Consumer- necessary ...
Page 27
DC Characteristics Table 4-2. DC Characteristics Recommended Operating conditions : VDD = 3.45V 0.15V, Tcase = 0 to 100 Symbol Parameter V Operating Voltage DD P Supply Power Internal Clock (Note 1) CLK V DAC ...
Page 28
ELECTRICAL SPECIFICATIONS Figure 4-1. Drive Level and Measurement Points for Switching Characteristics CLK: B Valid OUTPUTS: Output n INPUTS: LEGEND Maximum Output Delay Specification B - Minimum Output Delay Specification C - Minimum Input Setup Specification D - ...
Page 29
POWER ON SEQUENCE ply tra tio ...
Page 30
ELECTRICAL SPECIFICATIONS Table 4-4. PCI Bus AC Timing Name Parameter t1 PCI_CLKI to any output t2 Setup to PCICKLI t3 Hold from PCICLKI t4 PCICLKI to PCI_GNT# output valid t5 PCI_REQ# setup to PCI_CLKI T6 PCI_REQ# hold to PCI_CLKI Table ...
Page 31
Table 4-6. SDRAM Bus AC Timing Name Parameter t46 MCLKI to MA[11:0] Output Valid t47 MCLKI to MWE# Output Valid t48 MCLKI to MD[63:0] Output Valid t49 MD[63:0] setup to MCKLI (no RDCLK) t50 MD[63:0] setup to MCKLI (RDCLK at ...
Page 32
ELECTRICAL SPECIFICATIONS Figure 4-2 ISA Cycle (ref table Table 4 ALE AEN Valid AENx 3 LA [23:17] Valid Address SA [19:0] CONTROL (Note 1) IOCS16# MCS16# IOCHRDY READ DATA WRITE DATA Note 1; Stands for SMEMR#, ...
Page 33
Table 4-9. ISA Bus AC Timing Name Parameter 4 11c Memory access to 16 bit ISA Slave - 4BCLK 4 11d Memory access to 8 bit ISA Slave - 2BCLK 4 11e Memory access to 8 bit ISA Slave - ...
Page 34
ELECTRICAL SPECIFICATIONS Table 4-9. ISA Bus AC Timing Name Parameter 4 25b Memory access to 16 bit ISA Slave Standard cycle 4 25d Memory access to 8 bit ISA Slave Standard cycle 4 25 SMEMR#, SMEMW# asserted before next ALE# ...
Page 35
Table 4-9. ISA Bus AC Timing Name Parameter 4 41c I/O access to 16 bit ISA Slave 4 41d I/O access to 8 bit ISA Slave 4 42 SA[19:0] SBHE valid to read data valid 4 42b Memory access to ...
Page 36
ELECTRICAL SPECIFICATIONS Table 4-9. ISA Bus AC Timing Name Parameter MEMW# negated to copy data float, 8 bit ISA Slave, odd Byte 4 64f by ISA Master IOW# negated to copy data float, 8 bit ISA Slave, odd Byte by ...
Page 37
MECHANICAL DATA 5.1 388-Pin Package Dimension The pin numbering for the STPC 388-pin Plastic BGA package is shown in Figure 5-1. Figure 5-1. 388-Pin PBGA Package - Top View ...
Page 38
MECHANICAL DATA Figure 5-2. 388-pin PBGA Package - PCB Dimensions A1 Ball Pad Corner A Table 5-1. 388-pin PBGA Package - PCB Dimensions Symbols Min A 34.95 35.00 B 1.22 1.27 C 0.58 0.63 D 1.57 1.62 E 0.15 0.20 ...
Page 39
Figure 5-3. 388-pin PBGA Package - Dimensions C Solderball A Table 5-2. 388-pin PBGA Package - Dimensions Symbols Min A 0.50 0.56 B 1.12 1.17 C 0.60 0.76 D 0.52 0.53 E 0.63 0.78 F 0.60 0.63 G 30.0 F ...
Page 40
MECHANICAL DATA 5.2 388-Pin Package thermal data 388-pin PBGA package has a Power Dissipation Capability of 4.5W which increases to 6W when used with a Heatsink. Figure 5-4. 388-Pin PBGA structure Signal layers Figure 5-5. Thermal dissipation without heatsink Board ...
Page 41
Figure 5-6. Thermal dissipation with heatsink Board Ambient Rca Case Rjc Board Junction Rjb Board Rba Ambient Board dimensions: Junction - 10 12 layers (2 for signals, 1 GND, 1VCC) The PBGA is centered on ...
Page 42
BOARD LAYOUT 6. BOARD LAYOUT 6.1 Thermal dissipation Thermal dissipation of the STPC depends mainly on supply voltage result, when the system does not need to work at 3.45V interesting to reduce the voltage to 3.15V, ...
Page 43
When considering thermal dissipation, the most important - and not the more obvious - part of the layout is the connection between the ground balls and the ground layer. A 1-wire connection is shown in Figure 6-2. The use of ...
Page 44
BOARD LAYOUT Figure 6-4. Optimum layout for central ground ball The PBGA Package dissipates also through pe- ripheral ground balls. When a heat sink is placed on the device, heat is more uniformely spread throughout the moulding increasing heat dissipa- ...
Page 45
Figure 6-5. Global ground layout for good thermal dissipation Figure 6-6. Bottom side layout and decoupling Ground plane for thermal dissipation Via to ground layer Issue 1.1 - October 16, 2000 BOARD LAYOUT Via to ground layer Ground pad 45/59 ...
Page 46
BOARD LAYOUT Figure 6-7. Use of metal plate for thermal dissipation Metal planes Figure 6-8. Shielding signals ground pad 46/59 Die ground ring shielded signal line ground pad shielded signal lines Issue 1.1 - October 16, 2000 Board Thermal conductor ...
Page 47
Memory interface 6.3.1 Introduction In order to achieve SDRAM memory interfaces which work at clock frequencies of 100MHz and above, careful consideration has to be given to the timing of the interface with all the various electrical and physical ...
Page 48
BOARD LAYOUT Figure 6-10. DIMM placement from a low skew clock driver with matched routing lengths. This is shown inFigure 6-11. Figure 6-11. Clock routing Low skew clock driver: MCLKO * No additionnal 75mm when SDRAM directly soldered on board ...
Page 49
For designs which use SDRAMs directly mounted on the motherboard PCB all the clock trace lengths should be matched exactly. The DIMM sockets should be populated starting with the furthest DIMM from the STPC device first (DIMM1). There are 2 ...
Page 50
BOARD LAYOUT 6.3.4 Address & Control Signals This group encompasses the memory address MA[10:0], bank address BA[0], RAS, CAS and write enable WE signals. The load of the DIMM module on these signals is the most important one and depends ...
Page 51
Chip Select Signals (CS#[3:0]) There are 4 chip select pins per DIMM. Chip se- lects 0 and 2 are always used to select the first Figure 6-15. CS# equivalent circuit row of SDRAMs and chip selects 1 and 3 ...
Page 52
BOARD LAYOUT 6.3.6 Data Write (MD[63:0]) The load on the data signals is much lower than the address/control signals for an unbuffered DIMM. For a registered DIMM the data signals are the only memory pins of the DIMM which are ...
Page 53
Data Mask (DQM[7:0]) The data mask load is quite similar to that of the data signals. 6.3.9 Summary For unbuffered DIMMs the address/control signals will be the most critical for timing. The simulations show that for these signals the ...
Page 54
MCLKI MCLKO (Each signal needs it’s own line) MA[10:0] BA0 (MA[11]) CS0# WE# CAS# RAS# MCLK0A 16 MBit 16-bit wide MD DQM DQM [63:48] [7:6] [5:4] DQM# MD[63:0] Reference Knot MCLK0C MCLK0B 16 MBit 16 MBit 16-bit wide 16-bit wide ...
Page 55
MCLKI MCLKI MCKLO MCKLO MCLK0/1 Clock Buffer Clock Buffer MCLK2/3 Compulsary Compulsary (Each signal needs it’s own line) MA[10:0] BA0 (MA[11]) MCLK0A MCLK0B MCLK1A CS0#,2#, WE# CAS#, RAS# 16 MBit 16 MBit 16 MBit 8-bit wide 8-bit wide 8-bit wide ...
Page 56
BOARD LAYOUT Table 6-1. Standard Memory DIMM Pinout Memory Banks pin 16Mbit(2 banks) number ... MA[10:0] 123 126 39 122 BA0(MA11) Table 6-2. Address Mapping Address Mapping: 16 Mbit - 2 banks STPC I/F BA0(MA11) MA10 MA9 RAS ADDRESS A11 ...
Page 57
... ORDERING DATA 7.1 Ordering Codes STMicroelectronics Prefix Product Family PC: PC Compatible Product ID C03: Consumer-S Core Speed 66: 66MHz 75: 75MHz 90: 90MHz Package BT: 388 Overmoulded BGA Temperature Range C: Commercial Case Temperature (Tcase +100 C I: Industrial Case Temperature (Tcase +100 C Operating Voltage 3 : 3.45V 0. ...
Page 58
... ORDERING DATA 7.2 Available Part Numbers Core Frequency Part Number ( MHz ) STPCC0375BTC3 75 STPCC0390BTC3 90 58/59 CPU Mode Tcase Range ( +100 X1 Issue 1.1 - October 16, 2000 Operating Voltage ( V ) 3.45V 0.3V ...
Page 59
... N o license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...