MC9S08GB60ACFUE Freescale, MC9S08GB60ACFUE Datasheet - Page 112

• Manufacturer Part Number: MC9S08GB60ACFUE
• Manufacturer: Freescale

Specifications of MC9S08GB60ACFUE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8/2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

Internal Clock Generator (S08ICGV2)
In FEE mode, the reference clock is derived from the external reference clock ICGERCLK, and the FLL
loop will attempt to lock the ICGDCLK frequency to the desired value, as selected by the MFD bits. To
run in FEE mode, there must be a working 32 kHz–100 kHz or 2 MHz–10 MHz external clock source. The
maximum external clock frequency is limited to 10 MHz in FEE mode to prevent over-clocking the DCO.
The minimum multiplier for the FLL, from
operational limit of the DCO, the reference clock cannot be any faster than 10 MHz.
7.3.5.1
FEE unlocked is entered when FEE is entered and the count error (Δn) output from the subtractor is greater
than the maximum n
unlock condition.
The ICG will remain in this state while the count error (Δn) is greater than the maximum n
the minimum n
In this state, the pulse counter, subtractor, digital loop filter, and DCO form a closed loop and attempt to
lock it according to their operational descriptions later in this section. Upon entering this state and until
the FLL becomes locked, the output clock signal ICGOUT frequency is given by f
extra divide by two prevents frequency overshoots during the initial locking process from exceeding
chip-level maximum frequency specifications. As soon as the FLL has locked, if an unexpected loss of
lock causes it to re-enter the unlocked state while the ICG remains in FEE mode, the output clock signal
ICGOUT frequency is given by f
7.3.5.2
FEE locked is entered from FEE unlocked when the count error (Δn) is less than n
than n
condition. The output clock signal ICGOUT frequency is given by f
locked, the filter value is only updated once every four comparison cycles. The update made is an average
of the error measurements taken in the four previous comparisons.
7.3.6
To determine the FLL locked and loss-of-lock conditions, the pulse counter counts the pulses of the DCO
for one comparison cycle (see
the subtractor. The subtractor compares this value to the value in MFD and produces a count error, Δn. To
achieve locked status, Δn must be between n
must stay between n
unexpectedly, the LOLS status bit is set and remains set until acknowledged or until the MCU is reset.
LOLS is cleared by reading ICGS1 then writing 1 to ICGIF (LOLRE = 0), or by a loss-of-lock induced
reset (LOLRE = 1), or by any MCU reset.
If the ICG enters the off state due to stop mode when ENBDM = OSCSTEN = 0, the FLL loses locked
status (LOCK is cleared), but LOLS remains unchanged because this is not an unexpected loss-of-lock
condition. Though it would be unusual, if ENBDM is cleared to 0 while the MCU is in stop, the ICG enters
112
lock
(min) for a given number of samples, as required by the lock detector to detect the lock
FLL Lock and Loss-of-Lock Detection
FLL Engaged External Unlocked
FLL Engaged External Locked
lock
, as required by the lock detector to detect the lock condition.
unlock
unlock
(min) and n
or less than the minimum n
Table 7-2
ICGDCLK
MC9S08GB60A Data Sheet, Rev. 2
unlock
for explanation of a comparison cycle) and passes this number to
/ R.
Table
lock
(max) to remain locked. If Δn goes outside this range
(min) and n
7-7, is 4. Because 4 X 10 MHz is 40 MHz, which is the
unlock
, as required by the lock detector to detect the
lock
(max). As soon as the FLL has locked, Δn
ICGDCLK
/R. In FLL engaged external
ICGDCLK
lock
Freescale Semiconductor
(max) and greater
lock
/ (2×R). This
or less than