MC9S08GB60ACFUE Freescale, MC9S08GB60ACFUE Datasheet - Page 95

• Manufacturer Part Number: MC9S08GB60ACFUE
• Manufacturer: Freescale

Specifications of MC9S08GB60ACFUE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8/2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

6.6.4
Port D includes eight pins shared between general-purpose I/O, TPM1, and TPM2. Port D pins used as
general-purpose I/O pins are controlled by the port D data (PTDD), data direction (PTDDD), pullup enable
(PTDPE), and slew rate control (PTDSE) registers.
If a TPM takes control of a port D pin, the corresponding PTDDD bit is ignored. When the TPM is in
output compare mode, the corresponding PTDSE can be used to provide slew rate on the pin. When the
TPM is in input capture mode, the corresponding PTDPE can be used, provided the corresponding PTDDD
bit is 0, to provide a pullup device on the pin.
Reads of PTDD will return the logic value of the corresponding pin, provided PTDDD is 0.
Freescale Semiconductor
PTDPE[7:0]
PTDD[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
PTDPE7
PTDD7
Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD)
Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin. For port D
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
Pullup Enable for Port D Bits — For port D pins that are inputs, these read/write control bits determine whether
internal pullup devices are enabled. For port D pins that are configured as outputs, these bits are ignored and
the internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
0
0
7
7
PTDPE6
PTDD6
0
0
6
6
Figure 6-22. Pullup Enable for Port D (PTDPE)
Figure 6-21. Port D Data Register (PTDD)
Table 6-14. PTDPE Field Descriptions
Table 6-13. PTDD Field Descriptions
PTDPE5
PTDD5
MC9S08GB60A Data Sheet, Rev. 2
0
0
5
5
PTDPE4
PTDD4
0
0
4
4
Description
Description
PTDPE3
PTDD3
3
0
3
0
PTDPE2
PTDD2
0
0
2
2
Chapter 6 Parallel Input/Output
PTDPE1
PTDD1
0
0
1
1
PTDPE0
PTDD0
0
0
0
0
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