MC9S08SH4CTG Freescale, MC9S08SH4CTG Datasheet - Page 250
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MC9S08SH4CTG
Manufacturer Part Number
MC9S08SH4CTG
Description
Manufacturer
Freescale
Datasheet
1.MC9S08SH4CTG.pdf
(338 pages)
Specifications of MC9S08SH4CTG
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
256Byte
# I/os (max)
13
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
16
Package Type
TSSOP
Program Memory Type
Flash
Program Memory Size
4KB
Lead Free Status / RoHS Status
Compliant
Available stocks
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Manufacturer
Quantity
Price
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MC9S08SH4CTG
Manufacturer:
FREESCAL
Quantity:
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Chapter 16 Timer/PWM Module (S08TPMV3)
Reset clears the TPM counter registers. Writing any value to TPMxCNTH or TPMxCNTL also clears the
TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data
involved in the write.
When BDM is active, the timer counter is frozen (this is the value that will be read by user); the coherency
mechanism is frozen such that the buffer latches remain in the state they were in when the BDM became
active, even if one or both counter halves are read while BDM is active. This assures that if the user was
in the middle of reading a 16-bit register when BDM became active, it will read the appropriate value from
the other half of the 16-bit value after returning to normal execution.
In BDM mode, writing any value to TPMxSC, TPMxCNTH or TPMxCNTL registers resets the read
coherency mechanism of the TPMxCNTH:L registers, regardless of the data involved in the write.
16.3.3
The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM
counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock, and
the overflow flag (TOF) becomes set. Writing to TPMxMODH or TPMxMODL inhibits the TOF bit and
overflow interrupts until the other byte is written. Reset sets the TPM counter modulo registers to 0x0000
which results in a free running timer counter (modulo disabled).
Writing to either byte (TPMxMODH or TPMxMODL) latches the value into a buffer and the registers are
updated with the value of their write buffer according to the value of CLKSB:CLKSA bits, so:
The latching mechanism may be manually reset by writing to the TPMxSC address (whether BDM is
active or not).
250
Reset
Reset
•
•
W
W
R
R
If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written
If (CLKSB:CLKSA not = 0:0), then the registers are updated after both bytes were written, and the
TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If
the TPM counter is a free-running counter, the update is made when the TPM counter changes from
0xFFFE to 0xFFFF
Bit 15
Bit 7
TPM Counter Modulo Registers (TPMxMODH:TPMxMODL)
0
0
7
7
14
0
6
0
6
6
Figure 16-8. TPM Counter Register High (TPMxCNTH)
Figure 16-9. TPM Counter Register Low (TPMxCNTL)
MC9S08SH8 MCU Series Data Sheet, Rev. 3
Any write to TPMxCNTH clears the 16-bit counter
Any write to TPMxCNTL clears the 16-bit counter
13
5
0
5
5
0
12
0
4
0
4
4
11
0
3
0
3
3
10
0
2
0
2
2
Freescale Semiconductor
1
9
0
1
1
0
Bit 8
Bit 0
0
0
0
0
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