S9S08SG16E1CTJ Freescale, S9S08SG16E1CTJ Datasheet - Page 265
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S9S08SG16E1CTJ
Manufacturer Part Number
S9S08SG16E1CTJ
Description
Manufacturer
Freescale
Datasheet
1.S9S08SG16E1CTJ.pdf
(330 pages)
Specifications of S9S08SG16E1CTJ
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
SCI/SPI
Total Internal Ram Size
1KB
# I/os (max)
16
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
20
Package Type
TSSOP
Program Memory Type
Flash
Program Memory Size
16KB
Lead Free Status / RoHS Status
Compliant
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5. Center-Aligned PWM
6. Write to TPMxMODH:L registers in BDM mode
7. Update of EPWM signal when CLKSB:CLKSA = 00
— Center-Aligned PWM
— TPMxCnVH:L = TPMxMODH:L [SE110-TPM case 1]
— TPMxCnVH:L = (TPMxMODH:L - 1) [SE110-TPM case 2]
— TPMxCnVH:L is changed from 0x0000 to a non-zero value [SE110-TPM case 3 and 5]
— TPMxCnVH:L is changed from a non-zero value to 0x0000 [SE110-TPM case 4]
Registers
In the TPM v3 a write to TPMxSC register in BDM mode clears the write coherency mechanism
of TPMxMODH:L registers. Instead, in the TPM v2 this coherency mechanism is not cleared when
there is a write to TPMxSC register.
In the TPM v3 if CLKSB:CLKSA = 00, then the EPWM signal in the channel output is not update
(it is frozen while CLKSB:CLKSA = 00). Instead, in the TPM v2 the EPWM signal is updated at
the next rising edge of bus clock after a write to TPMxCnSC register.
The
v3 after the reset (CLKSB:CLKSA = 00) and if there is a write to TPMxCnSC register.
TPM counter changes from (TPMxMODH:L - 1) to (TPMxMODH:L). If the TPM counter is
a free-running counter, then this update is made when the TPM counter changes from $FFFE
to $FFFF. Instead, the TPM v2 makes this update after that the both bytes were written and
when the TPM counter changes from TPMxMODH:L to $0000.
In this mode and if (CLKSB:CLKSA not = 00), the TPM v3 updates the TPMxCnVH:L
registers with the value of their write buffer after that the both bytes were written and when the
TPM counter changes from (TPMxMODH:L - 1) to (TPMxMODH:L). If the TPM counter is
a free-running counter, then this update is made when the TPM counter changes from $FFFE
to $FFFF. Instead, the TPM v2 makes this update after that the both bytes were written and
when the TPM counter changes from TPMxMODH:L to (TPMxMODH:L - 1).
In this case, the TPM v3 produces 100% duty cycle. Instead, the TPM v2 produces 0% duty
cycle.
In this case, the TPM v3 produces almost 100% duty cycle. Instead, the TPM v2 produces 0%
duty cycle.
In this case, the TPM v3 waits for the start of a new PWM period to begin using the new duty
cycle setting. Instead, the TPM v2 changes the channel output at the middle of the current
PWM period (when the count reaches 0x0000).
In this case, the TPM v3 finishes the current PWM period using the old duty cycle setting.
Instead, the TPM v2 finishes the current PWM period using the new duty cycle setting.
Figure 16-17
(TPMxMODH:TPMxMODL))
and
Figure 16-18
(Section 16.4.2.4, “Center-Aligned PWM
(Section 16.4.2.4, “Center-Aligned PWM
MC9S08SG32 Data Sheet, Rev. 8
show when the EPWM signals generated by TPM v2 and TPM
(Section 16.3.3, “TPM Counter Modulo
Chapter 16 Timer/PWM Module (S08TPMV3)
Mode)
Mode)
265
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