MC9S08QG8CDTER Freescale, MC9S08QG8CDTER Datasheet - Page 249

• Manufacturer Part Number: MC9S08QG8CDTER
• Manufacturer: Freescale

Specifications of MC9S08QG8CDTER

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 512Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Lead Free Status / RoHS Status: Compliant

Figure 17-3
asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long
enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive
before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the
bit time. The host should sample the bit level about 10 cycles after it started the bit time.
Freescale Semiconductor
SYNCHRONIZATION
PERCEIVED START
PERCEIVED START
(TARGET MCU)
SPEEDUP PULSE
(TARGET MCU)
TO BKGD PIN
BDC CLOCK
HOST DRIVE
TARGET MCU
UNCERTAINTY
TRANSMIT 1
TRANSMIT 0
BDC CLOCK
OF BIT TIME
OF BIT TIME
BKGD PIN
HOST
HOST
shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is
Figure 17-3. BDC Target-to-Host Serial Bit Timing (Logic 1)
Figure 17-2. BDC Host-to-Target Serial Bit Timing
HIGH-IMPEDANCE
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
R-C RISE
10 CYCLES
HOST SAMPLES BKGD PIN
TARGET SENSES BIT LEVEL
10 CYCLES
10 CYCLES
HIGH-IMPEDANCE
HIGH-IMPEDANCE
EARLIEST START
EARLIEST START
OF NEXT BIT
OF NEXT BIT
Development Support
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