MC9S08QG8CDTER Freescale, MC9S08QG8CDTER Datasheet - Page 56

• Manufacturer Part Number: MC9S08QG8CDTER
• Manufacturer: Freescale

Specifications of MC9S08QG8CDTER

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 512Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 8KB
• Lead Free Status / RoHS Status: Compliant

Chapter 4 Memory Map and Register Definition
4.7
The FLASH module has six 8-bit registers in the high-page register space. Two locations (NVOPT,
NVPROT) in the nonvolatile register space in FLASH memory are copied into corresponding high-page
control registers (FOPT, FPROT) at reset. There is also an 8-byte comparison key in FLASH memory.
Refer to
section refers to registers and control bits only by their names. A Freescale Semiconductor-provided
equate or header file normally is used to translate these names into the appropriate absolute addresses.
4.7.1
Bit 7 of this register is a read-only status flag. Bits 6:0 may be read at any time but can be written only one
time. Before any erase or programming operations are possible, write to this register to set the frequency
of the clock for the nonvolatile memory system within acceptable limits.
Table 4-7
54
Reset
PRDIV8
DIVLD
Field
DIV
5:0
7
6
W
R
Table 4-3
FLASH Registers and Control Bits
shows the appropriate values for PRDIV8 and DIV for selected bus frequencies.
DIVLD
FLASH Clock Divider Register (FCDIV)
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for FLASH.
1 FCDIV has been written since reset; erase and program operations enabled for FLASH.
Prescale (Divide) FLASH Clock by 8
0 Clock input to the FLASH clock divider is the bus rate clock.
1 Clock input to the FLASH clock divider is the bus rate clock divided by 8.
Divisor for FLASH Clock Divider — The FLASH clock divider divides the bus rate clock (or the bus rate clock
divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV field plus one. The resulting frequency of the internal
FLASH clock must fall within the range of 200 kHz to 150 kHz for proper FLASH operations. Program/Erase
timing pulses are one cycle of this internal FLASH clock which corresponds to a range of 5 μs to 6.7 μs. The
automated programming logic uses an integer number of these pulses to complete an erase or program
operation. See
0
7
and
= Unimplemented or Reserved
PRDIV8
Table 4-4
Equation 4-1
0
6
if PRDIV8 = 1 — f
Figure 4-5. FLASH Clock Divider Register (FCDIV)
if PRDIV8 = 0 — f
Table 4-6. FCDIV Register Field Descriptions
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
for the absolute address assignments for all FLASH registers. This
and
0
5
Equation
FCLK
FCLK
4-2.
= f
0
4
= f
Bus
Description
Bus
÷ (8 × (DIV + 1))
÷ (DIV + 1)
3
0
DIV
0
2
Freescale Semiconductor
0
1
Eqn. 4-1
Eqn. 4-2
0
0