MC9328MX21VG Freescale, MC9328MX21VG Datasheet - Page 58

• Manufacturer Part Number: MC9328MX21VG
• Manufacturer: Freescale

Specifications of MC9328MX21VG

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
Specifications
3.17
3.17.1
To begin any communications with the DS2502, it is required that an initialization procedure be issued. A
reset pulse must be generated and then a presence pulse must be detected. The minimum reset pulse length
is 480 us. The bus master (one-wire) will generate this pulse, then after the DS2502 detects a rising edge
on the one-wire bus, it will wait 15-60 us before it will transmit back a presence pulse. The presence pulse
will exist for 60-240 us.
The timing diagram for this sequence is shown in
The reset pulse begins the initialization sequence and it is initiated when the RPP control register bit is set.
When the presence pulse is detected, this bit will be cleared. The presence pulse is used by the bus master
to determine if at least one DS2502 is connected. Software will determine if more than one DS2502 exists.
The one-wire will sample for the DS2502 presence pulse. The presence pulse is latched in the one-wire
58
Ref
No.
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
28
29
30
31
32
33
34
one-wire
BUS
Reset and Presence Pulses
(Tx) CK high to STXD high impedance
SRXD setup time before (Rx) CK low
SRXD hole time after (Rx) CK low
SRXD setup before (Tx) CK falling
SRXD
SRXD setup before (Tx) CK falling
SRXD
1-Wire Interface Timing
Reset Sequence with Reset Pulse Presence Pulse
old
old
Set RPP
fter
fter
Tx)
Tx)
h
h
Table 37. SSI to SSI3 Ports Timing Parameters (Continued)
Parameter
K falling
K falling
a
a
511 us
Synchronous External Clock Operation (SSI3 Ports)
Synchronous Internal Clock Operation (SSI3 Ports)
(
(
C
C
MC9328MX21 Technical Data, Rev. 3.4
Figure 46. 1-Wire Initialization
DS2502
waits
15-60us
Figure
Minimum
21.99
9.02
1.49
3.80
68us
46.
0
0
0
1.8 V ± 0.1 V
“presence pulse”
DS2502 Tx
60-240us
Maximum
16.46
–
–
–
–
–
–
One-Wire samples (set PST)
Minimum
21.99
7.29
1.49
3.80
0
0
0
3.0 V ± 0.3 V
512us
Freescale Semiconductor
Maximum
AutoClear RPP
14.97
Control Bit
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns