MC94MX21DVKN3 Freescale, MC94MX21DVKN3 Datasheet - Page 12

• Manufacturer Part Number: MC94MX21DVKN3
• Manufacturer: Freescale

Specifications of MC94MX21DVKN3

• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Signal Descriptions
12
Signal Name
UART2_RXD
UART3_RXD
UART4_RXD
UART2_TXD
UART2_RTS
UART2_CTS
UART3_TXD
UART3_RTS
UART3_CTS
UART4_TXD
UART4_RTS
UART4_CTS
SYS_CLK1
SYS_CLK2
SSI1_RXD
SSI2_RXD
SSI3_RXD
SSI1_TXD
SSI2_TXD
SSI3_TXD
SSI1_CLK
SSI2_CLK
SSI3_CLK
SAP_TXD
SAP_RXD
SAP_CLK
I2C_DATA
SSI1_FS
SSI2_FS
SSI3_FS
I2C_CLK
SAP_FS
OWIRE
Receive Data input signal. This signal is multiplexed with KP_ROW6 signal from KPP.
Transmit Data output signal. This signal is multiplexed with KP_COL6 signal from KPP.
Request to Send input signal. This signal is multiplexed with KP_ROW7 signal from KPP.
Clear to Send output signal. This signal is multiplexed with KP_COL7 signal from KPP.
Receive Data input signal. This signal is multiplexed with IR_RXD from FIRI.
Transmit Data output signal. This signal is multiplexed with IR_TXD from FIRI.
Request to Send input signal
Clear to Send output signal
Receive Data input signal which is multiplexed with USBH1_RXDP and USBH1_TXDP.
Transmit Data output signal which is multiplexed with USBH1_TXDM.
Request to Send input signal which is multiplexed with USBH1_FS and USBH1_RXDP.
Clear to Send output signal which is multiplexed with USBH1_TXDP and USBH1_RXDM.
Transmit serial data
Receive serial data
Frame Sync signal which is output in master and input in slave
SSI1 master clock. Multiplexed with TOUT.
Serial clock signal which is output in master or input in slave.
Transmit serial data signal
Receive serial data
Frame Sync signal which is output in master and input in slave.
SSI2 master clock. Multiplexed with TOUT.
Serial clock signal which is output in master or input in slave. Multiplexed with SLCDC2_CLK
Transmit serial data signal which is multiplexed with SLCDC2_CS
Receive serial data which is multiplexed with SLCDC2_RS
Frame Sync signal which is output in master and input in slave. Multiplexed with SLCDC2_D0.
Serial clock signal which is output in master or input in slave.
Transmit serial data
Receive serial data
Frame Sync signal which is output in master and input in slave.
I
I
1-Wire input and output signal. This signal is multiplexed with JTAG RTCK.
Serial clock signal which is output in master or input in slave
2
2
C Clock
C Data
Serial Audio Port – SSI (configurable to I
Table 2. i.MX21 Signal Descriptions (Continued)
MC94MX21 Technical Data, Rev. 1.5
1-Wire
I
2
C
Function/Notes
2
S protocol and AC97)
Freescale Semiconductor