MC94MX21DVKN3 Freescale, MC94MX21DVKN3 Datasheet - Page 93

• Manufacturer Part Number: MC94MX21DVKN3
• Manufacturer: Freescale

Specifications of MC94MX21DVKN3

• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

The limitation on pixel clock rise time/fall time is not specified. It should be calculated from the hold time
and setup time based on the following assumptions:
Rising-edge latch data
In most of case, duty cycle is 50 / 50, therefore
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
Falling-edge latch data
3.22.2
Figure 83
and the CSI is programmed to received data on the positive edge.
when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received
data in negative edge. The parameters for the timing diagrams are listed in
calculating the pixel clock rise and fall time is located in
Fall
Freescale Semiconductor
Time.”
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
positive duty cycle = 10 / 2 = 5ns
≥ max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
≥ max fall time allowed = 5 - 1 = 4ns
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
shows the timing diagram when the CMOS sensor output data is configured for negative edge
Non-Gated Clock Mode
VSYNC
DATA[7:0]
PIXCLK
Figure 83. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
MC94MX21 Technical Data, Rev. 1.
1
2
Valid Data
3
Section 3.22.3, “Calculation of Pixel Clock Rise/
Valid Data
Figure 84
4
6
Table
5
Valid Data
shows the timing diagram
45. The formula for
Specifications
93