MCIMX257CJM4A Freescale, MCIMX257CJM4A Datasheet - Page 109

• Manufacturer Part Number: MCIMX257CJM4A
• Manufacturer: Freescale

Specifications of MCIMX257CJM4A

• Lead Free Status / RoHS Status: Compliant

Note:
Freescale Semiconductor
• All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
• All timings are on pads when SSI is being used for data transfer.
• ”Tx” and “Rx” refer, respectively, to the transmit and receive sections of the SSI.
• For internal frame sync operation using external clock, the FS timing is the same as that of Tx data (for example, during AC97
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables figures.
mode of operation).
SS22
SS23
SS24
SS25
SS26
SS27
SS29
SS31
SS33
SS37
SS38
SS39
SS44
SS45
SS46
ID
(Tx/Rx) CK clock period
(Tx/Rx) CK clock high period
(Tx/Rx) CK clock rise time
(Tx/Rx) CK clock low period
(Tx/Rx) CK clock fall time
FS (bl) low/ high setup before (Tx) CK falling
FS (bl) low/ high setup before (Tx) CK falling
FS (wl) low/ high setup before (Tx) CK falling
FS (wl) low/ high setup before (Tx) CK falling
(Tx) CK high to STXD valid from high impedance
(Tx) CK high to STXD high/low
(Tx) CK high to STXD high impedance
SRXD setup before (Tx) CK falling
SRXD hold after (Tx) CK falling
SRXD rise/fall time
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6
Table 81. SSI Transmitter Timing with External Clock
Parameter
Synchronous External Clock Operation
External Clock Operation
–10.0
–10.0
Min.
81.4
36.0
36.0
10.0
10.0
10.0
2.0
—
—
—
—
—
—
Max.
15.0
15.0
15.0
15.0
15.0
6.0
6.0
6.0
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
109