MCIMX257CJM4A Freescale, MCIMX257CJM4A Datasheet - Page 68

• Manufacturer Part Number: MCIMX257CJM4A
• Manufacturer: Freescale

Specifications of MCIMX257CJM4A

• Lead Free Status / RoHS Status: Compliant

3.7.6.2
The i.MX25 NFC supports normal timing mode, using two Flash clock cycles for one access of RE and
WE. AC timings are provided as multiplications of the clock cycle and fixed delay.
Figure 37
under normal mode.
68
2
3
SDRAM CLK and DQS-related parameters are measured from the 50% point. That is, high is defined as 50% of the signal
value, and low is defined as 50% of the signal value. DDR SDRAM CLK parameters are measured at the crossing point of
SDCLK and SDCLK (inverted clock).
The value was calculated for an SDCLK frequency of 133 MHz, by the formula tQH = tHP – tQHS = min. (tCL,tCH) – tQHS =
0.45*tCK – tQHS = 0.45 * 7.5 – 0.45 = 2.925 ns
depicts the relative timing between NFC signals at the module level for different operations
NAND Flash Controller (NFC) Timing
NFWE
NFCLE
NFCE
NFWE
NFALE
NFIO[7:0]
NFCE
NFCLE
NFIO[7:0]
NFALE
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6
Table 53
Figure 34. Command Latch Cycle Timing Diagram
Figure 35. Address Latch Cycle Timing Diagram
describes the timing parameters (NF1–NF17) that are shown in the figures.
NF6
NF6
NF3
NF3
NF1
NF1
Command
NF8
Address
NF5
NF8
NF5
NF10
NF4
NF9
NF7
NF9
NF7
NF11
NF2
NF4
Figure 34
Freescale Semiconductor
through