PNX1301EH/G,557 Trident Microsystems, Inc., PNX1301EH/G,557 Datasheet - Page 475

• Manufacturer Part Number: PNX1301EH/G,557
• Manufacturer: Trident Microsystems, Inc.

Specifications of PNX1301EH/G,557

• Lead Free Status / RoHS Status: Supplier Unconfirmed

PNX1300/01/02/11 Data Book
ufixrz
SYNTAX
FUNCTION
DESCRIPTION
writes the result into rdest. Rounding toward zero is performed; the IEEE rounding mode bits in PCSW are ignored.
This is the preferred rounding mode for ANSI C. If rsrc1 is denormalized, zero is substituted before conversion, and
the IFZ flag in the PCSW is set. If
corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a
side-effect of any floating-point operation but can only be reset by an explicit
the PCSW exception flags occurs at the same time as rdest is written. If any other floating-point compute operations
update the PCSW at the same time, the net result in each exception flag is the logical OR of all simultaneous updates
ORed with the existing PCSW value for that exception flag.
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
A-177
r30 = 0x40400000 (3.0)
r35 = 0x40247ae1 (2.57)
r10 = 0,
r40 = 0xff4fffff (–3.402823466e+38)
r20 = 1,
r40 = 0xff4fffff (–3.402823466e+38)
r45 = 0x7f800000 (+INF))
r50 = 0xbfc147ae (-1.51)
r60 = 0x00400000 (5.877471754e-39)
r70 = 0xffffffff (QNaN)
r80 = 0xffbfffff (SNaN)
The
The
The
[ IF rguard ] ufixrz rsrc1 → rdest
if rguard then {
}
rdest ← (unsigned long) ((float)rsrc1)
ufixrz
ufixrzflags
ufixrz
Initial Values
operation converts the single-precision IEEE floating-point value in rsrc1 to an unsigned integer and
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
PRELIMINARY SPECIFICATION
operation computes the exception flags that would result from an individual
ufixrz r30 → r100
ufixrz r35 → r102
IF r10 ufixrz r40 → r105
IF r20 ufixrz r40 → r110
ufixrz r45 → r112
ufixrz r50 → r115
ufixrz r60 → r117
ufixrz r70 → r120
ufixrz r80 → r122
ufixrz
Convert floating-point to unsigned integer with
causes an IEEE exception, such as overflow or underflow, the
Operation
writepcsw
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
r100 ← 3
r102 ← 2, INX flag set
no change, since guard is false
r110 ← 0x0, INV flag set
r112 ← 0xffffffff (2
r115 ← 0, INV flag set
r117 ← 0, IFZ set
r120 ← 0, INV flag set
r122 ← 0, INV flag set
ifixieee ufixieee ifixrz
round toward zero
Philips Semiconductors
ATTRIBUTES
operation. The update of
SEE ALSO
Result
32
ufixrz
-1), INV flag set
.
125
1, 4
falu
No
—
1
3