PNX1301EH/G,557 Trident Microsystems, Inc., PNX1301EH/G,557 Datasheet - Page 60

• Manufacturer Part Number: PNX1301EH/G,557
• Manufacturer: Trident Microsystems, Inc.

Specifications of PNX1301EH/G,557

• Lead Free Status / RoHS Status: Supplier Unconfirmed

PNX1300/01/02/11 Data Book
3.1.7
The architecture supports the notion of 'unsigned inte-
gers' and 'signed integers.' Signed integers use the stan-
dard two’s-complement representation.
Arithmetic on integers does not generate traps. If a result
is not representable, the bit pattern returned is operation
specific, as defined in the individual operation description
section. The typical cases are:
• Wrap around for regular add- and subtract-type oper-
• Clamping against the minimum or maximum repre-
• Returning the least significant 32-bit value of a 64-bit
3.1.8
The PNX1300 architecture supports single precision (32-
bit) IEEE-754 floating point arithmetic.
All arithmetic conforms to the IEEE-754 standard in
flush-to-zero mode.
All floating point compute operations round according to
the current setting of the PCSW IEEE mode field. The
current setting of the field determines result rounding (to
nearest, to zero, to positive infinity, to negative infinity).
Conversions from float to integer/unsigned are available
in two forms: a PCSW rounding-mode-observing form
and an ANSI-C-specific-rounding form. The ANSI-C-
specific form forces round to zero regardless of the
PCSW IEEE rounding mode. Conversion from integer/
unsigned to float always observes the IEEE rounding
mode.
Floating point exceptions are supported with two mecha-
nisms. Each individual floating point operation (e.g. fadd)
has a counterpart operation (faddflags) that computes
the exception flag values. These operations can be used
for precise exception identification
nism uses the ‘sticky’ exception bits in the PCSW that
collect aggregate exception events. The PCSW excep-
tion bits can selectively invoke CPU exception handling.
See
Table 3-3
made in PNX1300’s floating point implementation.
3.1.9
The addressing modes shown in
ed by the DSPCPU architecture (store operations allow
only displacement mode).
3-4
1.
ations.
sentable value for DSP-type operations.
result (e.g., integer/unsigned multiply).
Section 3.5.2, “EXC (Exceptions).”
This mechanism allows precise exception identification
in the context of our multi-issue microprocessor core—
where many floating point operations may issue simul-
taneously—at the expense of additional operations
generated by the compiler. It also allows the compiler to
issue compute operations speculatively and compute
exceptions precisely.
Integer Representation
Floating Point Representation
Addressing Modes
shows the representation choices that were
PRELIMINARY SPECIFICATION
Table 3-4
1
. The second mecha-
are support-
Table 3-3. Special Float Value Representation
Table 3-4. Addressing Modes
In these addressing modes, R[i] indicates one of the gen-
eral purpose registers. The scale factor applied (1/2/4) is
Table 3-5. Minimum values for implementation-
dependent addressing mode components
equal to the size of the item loaded or stored, i.e. 1 for a
byte operation, two for a 16-bit operation and four for a
32-bit operation. The range of valid 'i', 'j' and 'k' values
may differ between implementations of the architecture;
the minimum values for implementation-dependent char-
acteristics are shown in
Note that the assembly code specifies the true displace-
ment, and not the value to be scaled. For example,
‘ld32d(–8) r3’ loads a 32-bit value from address (r3 – 8).
This is encoded in the binary operation pattern as a –2 in
the seven-bit field by the assembler. At runtime, the
scale factor four is applied to reconstruct the intended
displacement of –8.
3.1.10
The DSPCPU architecture expressly does not support
binary compatibility between family members. The ANSI
C compiler ensures that all family members are compat-
ible at the source-code level.
+inf
-inf
self generated qNaN 0xffffffff
result of operation
on any NaN argu-
ment
signalling NaN
R[i] + scaled(#j)
R[i] + R[k]
R[i] + scaled(R[k])
Parameter
‘i’ and ‘k’
‘j’
Mode
Item
Software Compatibility
0..127 (i.e., each implementation has at least 128
registers)
-64..63 (i.e., displacements will be at least 7 bits
long and signed)
Suffix
0x7f800000
0xff800000
argument | 0x00400000 (forcing the
NaN to be quiet)
never generated by PNX1300,
accepted as per IEEE-754
d
x
r
Table
Minimum Range
Philips Semiconductors
Load & Store
Applies to
Load only
Load only
3-5.
Representation
Displacement
Index
Scaled index
Name