PNX1301EH/G,557 Trident Microsystems, Inc., PNX1301EH/G,557 Datasheet - Page 505

• Manufacturer Part Number: PNX1301EH/G,557
• Manufacturer: Trident Microsystems, Inc.

Specifications of PNX1301EH/G,557

• Lead Free Status / RoHS Status: Supplier Unconfirmed

PNX1300/01/02/11 Data Book
writepcsw
SYNTAX
FUNCTION
DESCRIPTION
using rsrc2 as a mask. A bit in PCSW is affected by
value of any bit in PCSW with a corresponding 0-bit in rsrc2 will not be changed by
hardware update (e.g., when a floating-point exception is raised) and a software update (through a
coincide, the PCSW bits currently being updated by hardware will reflect the hardware-determined value while the bits
not being affected by hardware will reflect the value in the
below. The programmer should take care not to alter UNDEF fields in the PCSW.
occur during program execution. Thus,
operation and to clear fields that record events; this operation can also be used to restore state before resuming an
idled task in a multi-tasking environment. Note: The latency of writepcsw is 1, i.e. the PCSW reflects the new value in
the next cycle. But it takes additional 3 cycles for updates to the exception flags and exception enable bits to take
effect in the hardware. Therefore 3 delay slots / nops shall be inserted between writepcsw and the next interruptible
jump, if exception flags or enable bits are changed. This guarantees that the new state is recognized in the interrupt
logic during execution of the ijump.
modification of PCSW. If the LSB of rguard is 1, PCSW is written; otherwise, PCSW is unchanged.
EXAMPLES
A-207
exception trap enable
r30 = 0x100, r40 = 0x180
r20 = 0, r50 = 0x0, r60 = 0x400
r21 = 1, r50 = 0x0, r60 = 0x400
r70 = 0x80110000, r80 = 0xffff0000
Misaligned store exception
PCSW<31:16>
The
Fields in the PCSW have two chief purposes: to control aspects of processor operation and to record events that
The
[ IF rguard ] writepcsw rsrc1 rsrc2
if rguard then {
}
PCSW<15:0>
Write back error trap enable
Misaligned store
PCSW ← (PCSW & ~rsrc2) | (rsrc1 & rsrc2)
writepcsw
writepcsw
Reserved exception
Write back error
Initial Values
MSE
MSE
TRP
15
31
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
copies the value of rsrc1 to the PCSW (Program Control and Status Word) processor register
WBE RSE
WBE
PRELIMINARY SPECIFICATION
TRP
14
30
Count stalls (1 ⇒ Yes)
Reserved exception
trap enable
TRP
RSE
29
13
U N D E F
writepcsw r30 r40
IF r20 writepcsw r50 r60
IF r21 writepcsw r50 r60
writepcsw r70 r80
12
28
U N D E F
writepcsw
CS
11
27
TFE
IEN
10
26
Operation
Trap on first exit
Interrupt enable (1 ⇒ allow interrupts)
writepcsw
BSX IEEE MODE OFZ
Write program control and status word
can be used to effect changes in some aspects of processor
25
9
U N D E F I N E D
Byte sex (1 ⇒ little endian)
writepcsw
8
only if the corresponding bit in rsrc2 is set to 1; the
IEEE rounding mode
0 ⇒ to nearest, 1 ⇒ to zero, 2 ⇒ to positive, 3 ⇒ to negative
23
7
TRP
OFZ
22
6
PCSW.IEEE MODE = to positive infinity
no change, since guard is false
PCSW.IEN = 0 (disable interrupts)
enable trap on MSE, INV and DBZ exclusively
operand. The layout of PCSW is shown
TRP
IFZ
IFZ
21
5
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
FP exception trap-enable bits
readpcsw fadd faddflags
ijmpf cycles hicycles
TRP
INV
INV
20
4
Philips Semiconductors
FP exceptions
writepcsw
OVF
OVF
TRP
ATTRIBUTES
Result
19
3
SEE ALSO
UNF
TRP
UNF
18
2
writepcsw
. Whenever a
TRP
INX
INX
17
1
fcomp
161
No
—
1
1
3
DBZ
TRP
DBZ
16
0
)