SAA7111AH NXP Semiconductors, SAA7111AH Datasheet - Page 7

• Manufacturer Part Number: SAA7111AH
• Manufacturer: NXP Semiconductors

Specifications of SAA7111AH

• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
1998 May 15
RTS0
VS
HREF
V
V
VPO
(15 to 10)
V
V
VPO
(9 to 0)
FEI
GPSW
XTAL
XTALI
V
V
TRST
TCK
RTCO
SYMBOL
SSD3
DDD3
SSD2
DDD2
SSD1
DDD1
Enhanced Video Input Processor (EVIP)
(L)QFP64
34 to 39
42 to 51
PIN
29
30
31
32
33
40
41
52
53
54
55
56
57
58
59
60
I/O/P
O
O
O
O
O
O
O
O
P
P
P
P
P
P
I
I
I
I
Two functions output; controlled by I
RTSE0 = 0: odd/even field identification (HIGH = odd field). RTSE0 = 1: vertical
locked indicator; a HIGH state indicates that the internal Vertical Noise Limiter (VNL)
has locked.
Vertical sync signal (enabled via I
sync with respect to the YUV output. The HIGH period of this signal is approximately
six lines if the VNL function is active. The positive slope contains the phase
information for a deflection controller.
Horizontal reference output signal (enabled via I
to indicate data on the digital YUV bus. The positive slope marks the beginning of a
new active line. The HIGH period of HREF is 720 Y samples long. HREF can be used
to synchronize data multiplexer/demultiplexer. HREF is also present during the
vertical blanking interval.
Ground for digital supply voltage input 3.
Digital supply voltage 3 (+3.3 V).
Digital VPO-bus (Video Port Out) signal; higher bits of the 16-bit VPO-bus or the
16-bit RGB-bus output signal. The output data rate, the format and multiplexing
scheme of the VPO-bus are controlled via I
bit VIPB = 1 the six MSBs of the digitized input signal are connected to these outputs,
configured by the I
LUMA
Ground for digital supply voltage input 2.
Digital supply voltage 2 (+3.3 V).
Digital VPO-bus output signal; lower bits of the 16-bit YUV-bus or the 16-bit RGB-bus
output signal. The output data rate, the format and multiplexing schema of the
VPO-bus are controlled via I
the digitized input signal are connected to these outputs, configured by the I
‘MODE’ bits (see Figs 33 to 40): LUMA
CHROMA
Fast enable input signal (active LOW); this signal is used to control fast switching on
the digital YUV-bus. A HIGH at this input forces the IC to set its Y and UV outputs to
the high impedance state.
General purpose switch output; the state of this signal is set via I
the levels are TTL compatible.
Second terminal of crystal oscillator; not connected if external clock signal is used.
Input terminal for 24.576 MHz crystal oscillator or connection of external oscillator
with CMOS compatible square wave clock signal.
Ground for digital supply voltage input 1.
Digital supply voltage input 1 (+3.3 V).
Test reset input not (active LOW), for boundary scan test; notes 1, 2 and 3.
Test clock for boundary scan test; note 1.
Real time control output: contains information about actual system clock frequency,
subcarrier frequency and phase and PAL sequence.
VPO15 to VPO8, CHROMA
VPO7 to VPO0.
2
C-bus ‘MODE’ bits (see Figs 33 to 40):
7
2
C-bus bits OFTS0 and OFTS1. If I
2
C-bus bit OEHV); this signal indicates the vertical
DESCRIPTION
2
C-bus bit RTSE0.
VPO7 to VPO0.
VPO15 to VPO8,
2
C-bus bits OFTS0 and OFTS1. If I
2
C-bus bit OEHV); this signal is used
2
C-bus bit VIPB = 1
2
Product specification
C-bus control and
SAA7111A
2
C-bus
2
C-bus