AT94K05AL-25BQX Atmel, AT94K05AL-25BQX Datasheet - Page 56
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AT94K05AL-25BQX
Manufacturer Part Number
AT94K05AL-25BQX
Description
Manufacturer
Atmel
Datasheet
1.AT94K05AL-25BQX.pdf
(204 pages)
Specifications of AT94K05AL-25BQX
Device System Gates
5000
Propagation Delay Time
12.1ns
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / RoHS Status
Compliant
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AT94KAL Series FPSLIC
Table 4-4.
Note:
In summary, 16 select signals are sent to the FPGA for I/O addressing. These signals are
decoded from four base I/O Register addresses (FISUA..D) and extended to 16 with two bits
from the FPGA I/O Select Control Register, XFIS1 and XFIS0. The FPGA I/O read and write sig-
nals, FPGAIORE and FPGAIOWE, are qualified versions of the AVR IORE and IOWE signals.
Each will only be active if one of the four base I/O addresses is accessed.
Reset: all select lines become active and an FPGAIOWE strobe is enabled. This is to allow the
FPGA design to load zeros (8’h00) from the D-bus into appropriate registers.
Read or Write
I/O Address
FISUA $14 ($34)
FISUB $15 ($35)
FISUC $16 ($36)
FISUD $17 ($37)
1. Not available on AT94K05.
FPGA I/O Select Line Scheme
(1)
(1)
XFIS1
FISCR Register
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
XFIS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
15..12
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0010
0100
1000
FPGA I/O Select Lines
11..8
0000
0000
0000
0000
0000
0000
0000
0000
0001
0010
0100
1000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0010
0100
1000
0000
0000
0000
0000
0000
0000
0000
0000
7..4
1138I–FPSLI–1/08
0001
0010
0100
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
3..0
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