AT94K05AL-25BQX Atmel, AT94K05AL-25BQX Datasheet - Page 95
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AT94K05AL-25BQX
Manufacturer Part Number
AT94K05AL-25BQX
Description
Manufacturer
Atmel
Datasheet
1.AT94K05AL-25BQX.pdf
(204 pages)
Specifications of AT94K05AL-25BQX
Device System Gates
5000
Propagation Delay Time
12.1ns
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / RoHS Status
Compliant
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4.25.1
4.25.2
1138I–FPSLI–1/08
Timer/Counter 0 and 2 in PWM Mode
PWM Modes (Up/Down and Overflow)
Both Timer/Counters are realized as up or up/down (in PWM mode) counters with read and write
access. If the Timer/Counter is written to and a clock source is selected, it continues counting in
the timer clock cycle following the write operation.
Timer/Counter0 Output Compare Register – OCR0
Timer/Counter2 Output Compare Register – OCR2
The output compare registers are 8-bit read/write registers. The Timer/Counter Output Compare
Registers contains the data to be continuously compared with the Timer/Counter. Actions on
compare matches are specified in TCCR0 and TCCR2. A compare match does only occur if the
Timer/Counter counts to the OCR value. A software write that sets Timer/Counter and Output
Compare Register to the same value does not generate a compare match.
A compare match will set the compare interrupt flag in the CPU clock-cycle following the com-
pare event.
When PWM mode is selected, the Timer/Counter either wraps (overflows) when it reaches $FF
or it acts as an up/down counter.
If the up/down mode is selected, the Timer/Counter and the Output Compare Registers – OCR0
or OCR2 form an 8-bit, free-running, glitch-free and phase correct PWM with outputs on the
PE1(OC0/PWM0) or PE3(OC2/PWM2) pin.
If the overflow mode is selected, the Timer/Counter and the Output Compare Registers – OCR0
or OCR2 form an 8-bit, free-running and glitch-free PWM, operating with twice the speed of the
up/down counting mode.
The two different PWM modes are selected by the CTC0 or CTC2 bit in the Timer/Counter Con-
trol Registers – TCCR0 or TCCR2 respectively.
If CTC0/CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an up/down
counter, counting up from $00 to $FF, where it turns and counts down again to zero before the
cycle is repeated. When the counter value matches the contents of the Output Compare Regis-
ter, the PE1(OC0/PWM0) or PE3(OC2/PWM2) pin is set or cleared according to the settings of
the COMn1/COMn0 bits in the Timer/Counter Control Registers TCCR0 or TCCR2.
If CTC0/CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start count-
ing from $00 after reaching $FF. The PE1(OC0/PWM0) or PE3(OC2/PWM2) pin will be set or
cleared according to the settings of COMn1/COMn0 on a Timer/Counter overflow or when the
counter value matches the contents of the Output Compare Register. Refer to
details.
Bit
$31 ($51)
Read/Write
Initial Value
Bit
$22 ($42)
Read/Write
Initial Value
7
MSB
R/W
0
7
MSB
R/W
0
6
R/W
0
6
R/W
0
5
0
5
0
R/W
R/W
4
R/W
0
4
R/W
0
AT94KAL Series FPSLIC
3
R/W
0
3
R/W
0
2
R/W
0
2
R/W
0
1
R/W
0
1
R/W
0
0
LSB
R/W
0
0
LSB
R/W
0
Table 4-15
OCR0
OCR2
for
95
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