5962-8946805XC E2V, 5962-8946805XC Datasheet - Page 9

• Manufacturer Part Number: 5962-8946805XC
• Manufacturer: E2V

Specifications of 5962-8946805XC

• Lead Free Status / RoHS Status: Supplier Unconfirmed

DSCC FORM 2234
APR 97
Output data stable time
1/
2/
3/
4/
5/
6/
7/
8/
9/
10/ Transition is measured + 0.5 V from steady state voltage on the output from the 1.5 V level on
11/ This specification is the delay from synchronous register clock to internal feedback of the register output signal to the input
12/ Values guaranteed by design and are not tested.
13/ If data is applied to an I/O input for capture by a macrocell register, the I/O pin input set-up time minimums should be
14/ This specification is a measure of the delay associated with the internal register feedback path. This is the delay from
15/ This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine
from asynchronous clock
input
Test
These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
Tested initially and after any design or process changes that affect that parameter, and therefore shall be guaranteed to
the limits specified in table I.
For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed
one second.
Specified with device programmed as a 16-bit counter in each LAB. Tested with manufacturer test pattern and shall be
made available upon request.
AC tests are performed with input rise and fall times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0
to 3.0 V, and the output load on figure 4, circuit A.
This parameter is the delay from an input signal applied to a dedicated input pin to a combinatorial output on any output
pin. This delay assumes no expander terms are used to form the logic function.
This parameter is the delay from an input signal applied to an I/O macrocell pin to any output. This delay assumes no
This parameter is the delay from an input signal applied to a dedicated input pin to combinatorial output on any output pin.
for one pass through the expander logic.
This parameter is the delay from an input signal applied to an I/O macrocell pin to any output pin. This delay assumes
expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through
the expander logic.
of the LAB logic array and then to a combinatorial output. This delay assumes that no expanders are used, register is
synchronously clocked and all feedback is within the same LAB.
observed. These parameters are t
synchronous clock to LAB logic array input. This delay plus the register set-up time, t
an internal synchronous state machine configuration. This delay is for feedback within the same LAB.
configuration with external feedback can operate. It is assumed that all data inputs and feedback signals are applied to
dedicated inputs. All feedback is assumed to be local originating within the same LAB.
When this note is applied to any parameter specification it indicates that the signal (data, asynchronous clock,
asynchronous clear, and/or asynchronous preset) is applied to a dedicated input only and no signal path (either clock or
data) employs expander logic.
If an input signal is applied to an I/O pin an additional delay equal to t
dedicated input. If expanders are used add the maximum expander delay t
delay without expanders.
expander terms are used to form the logic function.
the input with the load on figure 4, circuit B.
This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay
DEFENSE SUPPLY CENTER COLUMBUS
12/ 26/
MICROCIRCUIT DRAWING
COLUMBUS, OHIO 43218-3990
STANDARD
│
│Symbol │
│
│
│
│t
│
│
│
TABLE I. Electrical performance characteristics - Continued.
AOH
S2
for synchronous operation and t
│
│
│
│
│See figure 5 5/
│
│
│
unless otherwise specified
-55°C≤T
4.5V ≤ V
Conditions
C
CC
≤+125°C
≤ 5.5V
SIZE
A
AS2
PIA
should be added to the comparable delay for a
for asynchronous operation.
│
│Group A
│subgroups │ types
│
│
│9, 10, 11
│
│
│
EXP
REVISION LEVEL
to the overall delay for the comparable
S1
, is the minimum internal period for
│
│Device │
│
│
│ All
│
│
│
C
│ Limits
│ Min │ Max │
│
│
│ 12
│
│
│
│
│
│
│
│
│
SHEET
5962-89468
│
│Unit
│
│
│ ns
│
│
│
9