AT77C104B-CB09YV Atmel, AT77C104B-CB09YV Datasheet - Page 23

• Manufacturer Part Number: AT77C104B-CB09YV
• Manufacturer: Atmel

Specifications of AT77C104B-CB09YV

• Lead Free Status / RoHS Status: Compliant

11. SPI Interface General Description
Figure 11-1. One Master with Several Slaves
11.1
5347F–BIOM–3/08
Master
Clock Phase and Polarity
Two communication busses are implemented in the device:
A synchronous Serial Port Interface (SPI) has been adopted for the two communication busses.
The SPI protocol is a slave/master full duplex synchronous serial communication. This protocol
uses three communication signals:
The slaves are selected by an input pin SS/ (Slave Select). A master can communicate with sev-
eral slaves.
The word length of the transferred data is fixed to 8 bits. The Most Significant Bit (MSB) is sent
first. For each 8-bit transfer, 8 bits are sent from the master to the slave and 8 bits transferred
from the slave to the master. Transfers are still synchronized with the communication clock
(SCK). Only the host can initialize transfers. To send data, the slave must wait for an access
from the master. When there is no transfer, a clock is not generated.
When a master is connected with several slaves, the signals SCK, MISO and MOSI are inter-
connected. Each slave SS/ is driven separately. Only one slave can be selected, the others
have their MISO tri-stated and ignore MOSI data.
The SS/ signal falls a half-period before the first clock edge, and rises a half-period after the last
clock edge.
During phase zero of the operation, the output data changes on the clock’s falling edge and the
input data is shifted in on the clock’s rising edge. In phase one of the operation, the output data
changes on the clock’s rising edge and is shifted in on the clock’s falling edge.
Polarity configures the clock’s idle level, which is high ('1') during polarity one of the operation
and low ('0') during polarity zero of the operation.
• The control interface, a slow bus that controls and reads the internal registers (status,
• The pixels’ acquisition interface, a fast bus that enables full pixel acquisition by the host.
• SCK (Serial Clock): the communication clock
• MOSI (Master Out Slave In): the data line from the master to the slave
• MISO (Master In Slave Out): the data line from the slave to the master
navigation, control...).
SS/1
Slave #1
SS/2
Slave #2
SS/3
Slave #3
AT77C104B
MOSI
MISO
SCK
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