SSTUA32866EC/G-T NXP Semiconductors, SSTUA32866EC/G-T Datasheet - Page 18

• Manufacturer Part Number: SSTUA32866EC/G-T
• Manufacturer: NXP Semiconductors

Specifications of SSTUA32866EC/G-T

• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 25
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 2V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SSTUA32866_2
Product data sheet
11.2 Data output slew rate measurement information
V
All input pulses are supplied by generators having the following characteristics:
PRR
Fig 16. Load circuit, HIGH-to-LOW slew measurement
Fig 17. Voltage waveforms, HIGH-to-LOW slew rate measurement
Fig 18. Load circuit, LOW-to-HIGH slew measurement
Fig 19. Voltage waveforms, LOW-to-HIGH slew rate measurement
DD
= 1.8 V
(1) C
(1) C
10 MHz; Z
L
L
includes probe and jig capacitance.
includes probe and jig capacitance.
0.1 V.
output
output
0
= 50 ; input slew rate = 1 V/ns
Rev. 02 — 26 March 2007
dv_r
1.8 V DDR2-667 configurable registered buffer with parity
dv_f
DUT
DUT
OUT
OUT
C
20 %
L
dt_r
= 10 pF
C
L
(1)
80 %
dt_f
80 %
= 10 pF
(1)
20 %, unless otherwise specified.
20 %
V
DD
R
test point
test point
R
002aaa379
002aaa377
L
L
= 50
= 50
SSTUA32866
002aaa380
002aaa378
V
V
V
V
© NXP B.V. 2007. All rights reserved.
OL
OH
OL
OH
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