SSTUA32866EC/G-T NXP Semiconductors, SSTUA32866EC/G-T Datasheet - Page 19

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SSTUA32866EC/G-T

Manufacturer Part Number
SSTUA32866EC/G-T
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SSTUA32866EC/G-T

Logic Family
SSTU
Logical Function
Registered Buffer
Number Of Elements
1
Number Of Bits
25
Number Of Inputs
25
Number Of Outputs
25
High Level Output Current
-8mA
Low Level Output Current
8mA
Propagation Delay Time
3ns
Operating Supply Voltage (typ)
1.8V
Operating Supply Voltage (max)
2V
Operating Supply Voltage (min)
1.7V
Clock-edge Trigger Type
Posit/Negat-Edge
Polarity
Non-Inverting
Technology
CMOS
Frequency (max)
450(Min)MHz
Mounting
Surface Mount
Pin Count
96
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
NXP Semiconductors
SSTUA32866_2
Product data sheet
11.3 Error output load circuit and voltage measurement information
V
All input pulses are supplied by generators having the following characteristics:
PRR
Fig 20. Load circuit, error output measurements
Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to
Fig 22. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect
DD
= 1.8 V
(1) C
10 MHz; Z
RESET input.
to clock inputs
L
includes probe and jig capacitance.
0.1 V.
0
waveform 1
= 50 ; input slew rate = 1 V/ns
waveform 2
RESET
output
timing
inputs
Rev. 02 — 26 March 2007
output
LVCMOS
1.8 V DDR2-667 configurable registered buffer with parity
t
DUT
PLH
OUT
V
t
HL
0.5V
ICR
0.15 V
DD
0.5V
DD
C
L
= 10 pF
V
ICR
(1)
20 %, unless otherwise specified.
V
DD
R
test point
002aaa500
L
002aaa502
= 1 k
SSTUA32866
002aaa501
V
V
V
V
0 V
V
0 V
DD
OL
i(p-p)
DD
OH
© NXP B.V. 2007. All rights reserved.
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