SSTV16857MTDX Fairchild Semiconductor, SSTV16857MTDX Datasheet - Page 4

• Manufacturer Part Number: SSTV16857MTDX
• Manufacturer: Fairchild Semiconductor

Specifications of SSTV16857MTDX

• Logic Family: SSTV
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 14
• Number Of Inputs: 14
• Number Of Outputs: 14
• High Level Output Current: -20mA
• Low Level Output Current: 20mA
• Package Type: TSSOP
• Propagation Delay Time: 5ns
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 200(Min)MHz
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Output Type: Standard
• Lead Free Status / RoHS Status: Compliant

www.fairchildsemi.com
I
R
R
R
V
V
V
V
V
V
V
V
V
V
V
V
I
I
I
R
R
R
DC Electrical Characteristics (SSTV16857)
DDD
DC Electrical Characteristics (SSTVN16857)
I
DD
DDD
IKL
IKH
IH-AC
IL-AC
IH-DC
IL-DC
IH
IL
ICR
I(PP)
OH
OL
OH
OL
O
OH
OL
O
Symbol
Symbol
'
'
Dynamic Operating Current
Clock Only
Dynamic Operating Current
per Data Input
Output HIGH On Resistance
Output LOW On Resistance
| R
Input LOW Clamp Voltage
Input HIGH Clamp Voltage
AC HIGH Level Input Voltage
AC LOW Level Input Voltage
DC HIGH Level Input Voltage
DC LOW Level Input Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
Common Mode Input Voltage Range
Peak to Peak Input Voltage
HIGH Level Output Voltage
LOW Level Output Voltage
Input Leakage Current
Static Standby
Static Operating
Dynamic Operating Current
Clock Only
Dynamic Operating Current
per Data Input
Output HIGH On Resistance
Output LOW On Resistance
| R
OH
OH
- R
- R
OL
OL
|
|
Parameter
Parameter
RESET
V
CK, CK Duty Cycle 50%
RESET
V
CK, CK Duty Cycle 50%
Data Input
Rate 50% Duty Cycle
I
I
I
I
I
Data Inputs
Data Inputs
Data Inputs
RESET
RESET
CLK, CLK
CLK, CLK
I
I
I
I
V
RESET
RESET
V
RESET
V
CK, CK Duty Cycle 50%
RESET
V
CK, CK Duty Cycle 50%
Data Input
Rate 50% Duty Cycle
I
I
I
Data Inputs
OH
OL
O
I
I
OH
OH
OL
OL
OH
OL
O
I
I
I
I
I
I


V
V
20 mA, T
V
V
V
V
20 mA, T
18 mA
18 mA
20 mA
100
16 mA
20 mA




IH(AC)
IH(AC)
DD
IH(AC)
IH(AC)
IH(AC)
20 mA
100
16 mA
20 mA
or GND
P
V
V
GND, I
V
V
V
Conditions
Conditions
A
DD
DD
P
DD
DD
DD
or V
or V
or V
or V
or V
A
½ Clock
½ Clock
A
A
, I
, I
, I
, I
, I
O
O
O
O
O
IL(AC)
IL(AC)
IL(AC)
IL(AC)
IL(AC)
O
25
25
4
0
0
q
0
0
0
q
C
0
C
(Continued)
(2.5V
2.3 to 2.7
2.3 to 2.7
2.5 to 2.7
2.5 to 2.7
2.5 to 2.7
2.5 to 2.7
V
V
(V)
2.7
2.5
(V)
2.5
2.5
2.5
2.5
2.7
2.7
2.7
2.5
DD
DD
d
V
DD
d
V
V
REF
REF
V
2.7V)
DD
0.97
1.95
Min
Min
360


1.7
7
7
7
7
310mV
150mV

0.2
V
V
REF
REF
Max
Max

1.53
0.35
r
3.5


0.7
0.2
90
20
20
10
25
90
20
20
15
15
1.2
5.0
4
4
310mV
150mV
P
P
P
P
Units
A/MHz
A/MHz
Units
A/MHz
A/MHz
mV
mA
P
P
:
:
:
:
:
:
V
V
V
V
V
V
V
V
V
V
V
A
A