LM050QC1T01 Sharp Electronics, LM050QC1T01 Datasheet - Page 20

• Manufacturer Part Number: LM050QC1T01
• Manufacturer: Sharp Electronics

Specifications of LM050QC1T01

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6-2. Display face configuration
6-3. Input data and control signal
The display consists of 320 × 3 (RGB) × 240 dots as shown in Fig.5. The interface is single panel with
single drive to be driven at 1 / 240 duty ratio.
The LCD driver (SEG Drv. shown in Fig.8) is 240 bits LSI, consisting of shift registers, latch circuits and
LCD driver circuits.
Input data for each row (320 dots × 3) will be sequentially transferred in the form of 8 bits parallel data
through shift registers from top left of the display together with clock signal (XCK). When input of one
row (320 dots × 3) is completed, the data will be latched in the form of parallel data corresponding to
the signal electrodes by the falling edge of latch signal (LP) then, the corresponding drive signals will be
transmitted to the (320 × 3) lines of column electrodes of the LCD panel by the LCD drive circuits.
At this time, scan start-up signal (YD) has been transferred from the scan signal driver (COM Drv. shown
in Fig.8) to the 1st row of scan electrodes, and the contents of the data signals are displayed on the 1st row
of the display face according to the combinations of voltages applied to the scan and column electrodes of
the LCD.
While the data of 1st row are being displayed, the data of 2nd row are entered. When the 2nd data for (320
× 3) dots have been transferred, they will be latched by the falling edge of LP, switching the display to
the 2nd row.
Such data input will be repeated up to the 240th row of each display segment, from upper row to lower
rows, to complete one frame of display by time-sharing method. Then data input proceeds to the next
display frame. YD generates scan signal to drive scan electrodes.
Since DC voltage, if applied to LCD panel, causes chemical reaction in LC materials, causing
deterioration of the materials, drive waveform shall be inverted at every display frame to prevent the
generation of such DC voltage. Control signal M plays such a role.
Because of the characteristics of the CMOS driver LSI, the power consumption of the display module
goes up with the clock cycle of XCK. To reduce data transfer speed of XCK clock the LSI has the system
of transferring 8 bits parallel data through the 8 lines of shift registers. Thanks to this system the power
consumption of the display module is reduced. In this circuit configuration, 8 bits display data shall input
to data input pins of D0 to 7.
SPEC No.
LU02204A
MODEL No.
LM050QC1T01
PAGE
18