ZT5524A1A Intel (CPU), ZT5524A1A Datasheet - Page 19

• Manufacturer Part Number: ZT5524A1A
• Manufacturer: Intel (CPU)

Specifications of ZT5524A1A

• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.3.8
2.3.9
2.3.10
Intel NetStructure
Note: Double-stacked DIMMs may be used only if they are within the 7.0 mm maximum thickness
All memory components and DIMMs used with the ZT 5524 / MPCBL5524 must comply with the
following PC SDRAM specifications:
imposed by the 0.3 DIMM socket spacing on the processor board.
Refer to the ZT 5524 / MPCBL5524 Compatibility Report available on the Intel website for a
complete list of compatible memory types. For more information, see
MPCBL5524 Product Page.”
Flash/BIOS Recovery
The ZT 5524 / MPCBL5524 incorporates 16 MBytes of on-board, programmable, BIOS Flash
memory. The BIOS resides in the first megabyte of flash. The FLASH.EXE utility allows you to
install an operating system image or any executable image into the remaining 15 MBytes of flash.
See the Intel NetStructure Embedded BIOS Software Manual for more information. See
Appendix E, “User Documentation.”
A second flash device is used as a BIOS recovery module. The ZT 5524 / MPCBL5524 can be
configured to use either device for boot control. When booting from the BIOS recovery module,
the BIOS update utility can access the onboard flash device by manipulating the system registers as
described in
and reset. See
Mezzanine Interface
The ZT 5524 / MPCBL5524 is available with the optional ZT 4901 mezzanine board. The ZT 4901
is a 6U mezzanine that provides Redundant Host (RH) functionality, dual Fibre Channel, dual 64/
66 PMC, and access to a second CompactPCI bus segment for bridging.
Intel designed the ZT 4901 to be used as a Redundant System Master for one or two bus segments,
a CompactPCI Bridge to a second CompactPCI bus segment, or as a standalone, add-on peripheral
mezzanine to the ZT 5524 / MPCBL5524. The CompactPCI bus interface supports a maximum of
seven CompactPCI peripheral cards at 33 MHz, or 5 peripheral slots in a 66 MHz system. See the
Intel NetStructure ZT 4901 Mezzanine Expansion Card Technical Product Specification for more
information. A link to this document is available in
The mezzanine interface is at J17 on the ZT 5524 / MPCBL5524. See
MPCBL5524 Connectors”
Power Ramp Circuitry
The ZT 5524 / MPCBL5524 features a hot swap controller with power ramp circuitry that enables
the board’s voltages to ramp in a controlled fashion. The power ramp circuitry eliminates any large
voltage or current spikes caused by removing or inserting hot swappable boards while the system is
still under power. This controlled ramping is a requirement of the CompactPCI Hot Swap
Specification, PICMG 2.1, Version 2.0.
•
•
®
PC SDRAM Specification (memory component specific)
PC SDRAM Registered DIMM Specification
ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS
Appendix B, “System Registers.”
Chapter 7, “BIOS Recovery,”
for more information.
for information on locating this document.
for more information.
The onboard flash is write protected on power up
Appendix E, “User
Appendix E, “ZT 5524 /
Appendix A, “ZT 5524 /
Documentation.”.
Introduction
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