ZT5524A1A Intel (CPU), ZT5524A1A Datasheet - Page 83

• Manufacturer Part Number: ZT5524A1A
• Manufacturer: Intel (CPU)

Specifications of ZT5524A1A

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Intel NetStructure
Table 49. CICBC Bit Descriptions
7:6
5
4
3
2
1
0
Bit
®
ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS
Reserved. Reserved for future use.
Arbiter Enable.
Read:
1 = the Arbiter is enabled
0 = the Arbiter is locked or disabled
Write:
When in Drone mode, this bit is cannot be written and is cleared so that the
arbiter remains locked.
When in Owner mode, this bit may be written to a 1 to enable the Arbiter or to
a 0 to lock the Arbiter.
This bit is reset by MRST or when SYSEN# is high (inactive).
Interrupts Enable. When this bit is set, the backplane interrupts are enabled if
the BIM is Owner.
When in Drone mode, this bit is cannot be written.
This bit is reset by MRST or when SYSEN# is high (inactive).
Switchover Request. When this bit is set, the CIC will request a switchover.
Available to RH Owner and RH Drone. This bit cannot be written when the
Mode Change bit is set.
This bit is reset by MRST or by the Mode Change status bit or when RH# is low
(asserted).
Transfer Now Command.
When in RH Drone mode, if this bit is written to 1, the CIC will immediately
remove ALT_SYSEN# from the bus owner.
When in RH owner mode, if this bit is written to 1, the CIC will immediately
assert ALT_SYSEN# to the RH. If there is an RH, this will result in a hostile
takeover.
Mode Lock. When this bit is set, the BIM is locked to whatever mode it is in.
When in Owner mode, if this bit is set, the CIC will not disable the arbiter in the
event of a fault.
When in Drone mode, if this bit is set, the CIC will not respond to a mode
change request and will not enter Owner mode, even if the Owner dies and is
removed from the backplane. This condition will result in a backplane reset,
however. RH Boards should have an onboard switch to preset this bit on when
a PCI reset occurs.
Backplane Bus Segment RESET MASK. When this bit is 1, the PCI RST# to
the backplane is masked and will not be asserted when in Owner Mode. The
RST# will not be asserted in Drone Mode even if this bit is cleared.
Description
None
R/W
R/W
R/W
W1
R/W
R/W
Access
System Registers
X
1: Owner
0: Drone
0
0
0
0(1)
0
Default
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