SI3210-FTR Silicon Laboratories Inc, SI3210-FTR Datasheet - Page 106

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SI3210-FTR

Manufacturer Part Number
SI3210-FTR
Description
SLIC 1-CH 60dB 41mA 3.3V/5V 38-Pin TSSOP T/R
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Datasheets

Specifications of SI3210-FTR

Package
38TSSOP
Number Of Channels Per Chip
1
Polarity Reversal
Yes
Longitudinal Balanced
60 dB
Loop Current
41 mA
Minimum Operating Supply Voltage
3.13 V
Typical Operating Supply Voltage
3.3|5 V
Typical Supply Current
88 mA
Function
Subscriber Line Interface Concept (SLIC), CODEC
Interface
PCM, SPI
Number Of Circuits
1
Voltage - Supply
3.3V, 5V
Current - Supply
88mA
Power (watts)
700mW
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
38-TSSOP
Includes
BORSCHT Functions, DTMF Generation and Decoding, FSK Generation, Pulse Metering Generation, Voice Loopback Test Modes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI3210-FTR
Manufacturer:
SILCONX
Quantity:
160
Part Number:
SI3210-FTR
Manufacturer:
SILICON
Quantity:
8 000
Part Number:
SI3210-FTR
Manufacturer:
SILICON LABS/芯科
Quantity:
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Si3210/Si3211
Register 86. Transistor 3 Current Sense
Reset settings = xxxx_xxxx
Register 87. Transistor 4 Current Sense
Reset settings = xxxx_xxxx
Register 88. Transistor 5 Current Sense
Reset settings = xxxx_xxxx
106
Name
Name
Name
Bit
7:0
Bit
7:0
Bit
7:0
Type
Type
Type
Bit
Bit
Bit
IQ3[7:0]
IQ4[7:0]
IQ5[7:0]
Name
Name
Name
D7
D7
D7
Transistor 3 Current Sense.
This register reports the real-time current through Q3. The range is 0 A (0x00) to
9.59 mA (0xFF) in 37.6 µA steps.
Transistor 4 Current Sense.
This register reports the real-time current through Q4. The range is 0 A (0x00) to
9.59 mA (0xFF) in 37.6 µA steps.
Transistor 5 Current Sense.
This register reports the real-time current through Q5. The range is 0 A (0x00) to
80.58 mA (0xFF) in .316 mA steps.
D6
D6
D6
D5
D5
D5
Rev. 1.45
D4
D4
D4
IQ3[7:0]
IQ4[7:0]
IQ5[7:0]
R
R
R
Function
Function
Function
D3
D3
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0

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