SAE81C91N Infineon Technologies, SAE81C91N Datasheet - Page 10

• Manufacturer Part Number: SAE81C91N
• Manufacturer: Infineon Technologies

Specifications of SAE81C91N

• Number Of Transceivers: 1
• Power Down Mode: Sleep
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Supplier Unconfirmed

SAE 81C90/91
07Feb95@09:05h Intermediate Version
Bit Stream Processor (BSP)
The bit-stream processor controls the entire protocol, differentiates between the frames types and
detects frame errors.
Error Management Logic (EML)
The error-management logic receives error messages from the BSP and, in turn, sends back
information about error state to the BSP and CIL.
Bit Timing Logic (BTL)
The bit-timing logic determines the timing of the bits and synchronizes with the edges of the bit
stream on the CAN bus.
Transceiver Control Logic (TCL)
The transceiver-control logic consists of programmable output driver, input comparator and input
multiplexer.
Clock Generator (CG)
The clock generator consists of an oscillator and a programmable divider. The oscillator can be fed
from an external quartz crystal, ceramic resonator or an external timing source. The permissible
crystal frequency is 1 to 20 MHz, and the external clock may be between 0 and 20 MHz. A
programmable frequency, dependent on the crystal clock, is available with the CLKOUT pin, e.g. for
the clocking of a host controller.
CPU Interface Logic (ClL)
The CPU interface logic controls the access of the host via the parallel or serial interface, interprets
the commands and outputs status and interrupt information.
Transmit Check
The CAN protocol ensures a very high integrity for the data transferred over the bus. The on-chip
path from the data stored in parallel to the serial bit stream is not protected by the protocol. To
eliminate any possible uncertainties at this point too, the SFCAN circuit incorporates a transmit-
check unit. This unit reads back a transmitted message via the normal receive path from the bus
interface and compares the data with those written into the message memory by the host controller.
If any inconsistency of the data is detected, the current message will be invalidated by an error
frame.
The transmit-check error counter TCEC is then incremented by 1. If this counter reaches 4 an error
interrupt (bit TCI in the INT register) is generated, provided that this has not been masked (bit ETCI
in the IMSK register). This count will also produce the Bus Off status.
The TCEC is set to 0 after a reset and can be read and also written for test purposes at any time.
Note: The transmit-check is an additional feature of the Siemens Full CAN Chip and is not part
of the CAN protocol.
Semiconductor Group
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