SAE81C91N Infineon Technologies, SAE81C91N Datasheet - Page 26

• Manufacturer Part Number: SAE81C91N
• Manufacturer: Infineon Technologies

Specifications of SAE81C91N

• Number Of Transceivers: 1
• Power Down Mode: Sleep
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Receive-Ready Registers
RRR2
Address: 05
Reset Value: 00
RRR1
Address: 04
Reset Value: 00
Bit(field)
RRn
These register bits can be reset by writing ’0’ to the respective bit, writing ’1’ has no effect. Bit RRn
is set when a message has arrived and been written into the memory location of message n. Setting
this bit by hardware can generate a receive interrupt, which can be blocked by bit RIMn in the
receive-interrupt-mask register.
Bits RRn must be reset by software.
Receive-Interrupt-Mask Registers
Setting bit RIMn enables a receive interrupt to be generated if the receive-ready bit RRn has been
set, i.e. a message has arrived and was written into the memory location of message n.
RIMR2
Address: 07
Reset Value: 00
RIMR1
Address: 06
Reset Value: 00
Bit(field)
RIMn
Note: Bit ERI in the interrupt-mask register IM blocks all receive interrupts, even if bits RIMn are
Semiconductor Group
set.
H
H
H
H
H
H
H
H
Function
Receive Ready Bit
’0’:
’1’:
Function
Receive Interrupt Mask Bit
’0’:
’1’:
RIM15
RR15
RIM7
RR7
No new message received in object n.
A new message has been received and stored in object n.
No interrupt upon reception of object n.
When a new message is stored in object n an interrupt is generated.
rw
rw
rw
rw
7
7
7
7
RIM14
RR14
RIM6
07Feb95@09:05h Intermediate Version
RR6
rw
rw
rw
rw
6
6
6
6
RIM13
RR13
RIM5
RR5
rw
rw
rw
rw
5
5
5
5
25
RIM12
RR12
RIM4
RR4
rw
rw
rw
rw
4
4
4
4
RIM11
RR11
RIM3
RR3
rw
rw
rw
rw
3
3
3
3
RIM10
RR10
RIM2
RR2
rw
rw
rw
rw
2
2
2
2
SAE 81C90/91
RIM9
RIM1
RR9
RR1
rw
rw
rw
rw
1
1
1
1
RIM8
RIM0
RR8
RR0
rw
rw
rw
rw
0
0
0
0