CY7C04312BV-133BGC Cypress Semiconductor Corp, CY7C04312BV-133BGC Datasheet - Page 27

• Manufacturer Part Number: CY7C04312BV-133BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C04312BV-133BGC

• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-06027 Rev. *A
capture set-up plus hold times. Once the data is captured, it is
possible to shift out the data by putting the TAP into the
Shift-DR state. This places the boundary scan register
between the TDI and TDO pins. If the TAP controller goes into
the Update-DR state, the sampled data will be updated.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
CLAMP
The optional CLAMP instruction allows the state of the signals
driven from QuadPort DSE device pins to be determined from
the boundary-scan register while the BYPASS register is
selected as the serial path between TDI and TDO. CLAMP
controls boundary cells to 1 or 0.
CYBIST
CYBIST instruction provides the user with a means of running
a user-accessible self-test function within the QuadPort DSE
device as a result of a single instruction. This permits all
components on a board that offer the CYBIST instruction to
execute their self-tests concurrently, providing a quick check
for the board. The QuadPort DSE device MBIST provides two
modes of operation once the TAP controller is loaded with the
CYBIST instruction:
Non-Debug Mode (Go-NoGo)
The non-debug mode is a go-nogo test used simply to run
BIST and obtain pass-fail information after the test is run. In
addition to that, the total number of failures encountered can
be obtained. This information is used to aid the debug mode
(explained next) of operation. The pass-fail information and
failure count is scanned out using the JTAG interface. An
MBIST Result Register (MRR) will be used to store the
pass-fail results. The MRR is a 25-bit register that will be
connected between TDI and TDO during the internal scan
(INT_SCAN) operation. The MRR will contain the total number
of fail read cycles of the entire MBIST sequence. MRR[0] (bit
0) is the Pass/Fail bit. A “1” indicates some type of failure
occurred, and a “0” indicates entire memory pass.
In order to run BIST in non-debug mode, the two-bit MBIST
Control Register (MCR) is loaded with the default value “00”,
and the TAP controller’s finite state machine (FSM), which is
synchronous to TCK, transitions to Run Test/Idle state. The
entire MBIST test will be performed with a deterministic
number of TCK cycles depending on the TCK and CLKBIST
frequency.
t
SPC is the Synchronization Padding Cycles (4–6 cycles).
m is a constant represents the number of read and write opera-
tions required to run MBIST algorithms (31195136).
Once the entire MBIST sequence is completed, supplying
extra TCK or CLKBIST cycles will have no effect on the MBIST
controller state or the pass-fail status.
Debug Mode
With the CYBIST instruction loaded and the MCR loaded with
the value of “01,” and the FSM transitions to RUN_TEST/IDLE
state, the MBIST goes into CYBIST-debug mode. The debug
mode will be used to provide complete failure analysis infor-
mation at the board level. It is recommended that the user runs
the non-debug mode first and then the debug mode in order to
save test time and to set an upper bound on the number of
scan outs that will be needed. The failure data will be scanned
out automatically once a failure occurs using the JTAG TAP
interface. The failure data will be represented by a 100-bit
packet given below. The 100-bit Memory Debug Register
(MDR) will be connected between TDI and TDO, and will be
shifted out on TDO, which is synchronized to TCK.
t
CYC
CYC
is total number of TCK cycles required to run MBIST.
=
t
--------------------------------------------
CYC
t
CYC
CLKBIST
TCK
m
+
SPC
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