CY7C04312BV-133BGC Cypress Semiconductor Corp, CY7C04312BV-133BGC Datasheet - Page 31

• Manufacturer Part Number: CY7C04312BV-133BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C04312BV-133BGC

• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-06027 Rev. *A
Table 5. Scan Registers Sizes
Table 6. Instruction Identification Codes
Table 7. MBIST Control States
Instruction (IR)
Bypass (BYR)
Identification (IDR)
MBIST Control (MCR)
MBIST Result (MRR)
MBIST Debug (MDR)
Boundary Scan (BSR)
EXTEST
BYPASS
IDCODE
HIGHZ
CLAMP
SAMPLE/PRELOAD
CYBIST
INT_SCAN
MCR_SCAN
RESERVED
States Code
Instruction
Register Name
000001
000010
000101
000100
000011
000110
000111
001100
001101
001111
0000
1111
0111
0110
0101
0001
1000
0010
0011
All other codes Seven combinations are reserved. Do not use other than the above.
movi_zeros
movi_1_upcnt
movi_0_upcnt
movi_1_downcnt
movi_0_downcnt
movi_read
mar2_zeros
mar2_1_upcnt
mar2_0_upcnt
mar2_1_downcnt
Code
State Name
4
1
32
2
25
100
392
Bit Size
Captures the Input/Output ring contents. Places the boundary scan register (BSR)
between the TDI and TDO.
Places the bypass register (BYR) between TDI and TDO.
Loads the ID register (IDR) with the vendor ID code and places the register
between TDI and TDO.
Places the BYR between TDI and TDO. Forces all QuadPort DSE device output
drivers to a High-Z state.
Controls boundary to 1/0. Uses BYR.
Captures the Input/Output ring contents. Places the boundary scan register (BSR)
between TDI and TDO.
Invokes MBIST. Places the MBIST Debug register (MDR) between TDI and TDO.
Scans out pass-fail information. Places MBIST Result Register (MRR) between TDI
and TDO.
Presets CYBIST mode. Places MBIST Control Register (MCR) between TDI and
TDO.
Port 1 write all zeros to the QuadPort DSE device memory using Moving
Inversion Algorithm (MIA).
Up count from 0 to 64K (depth of QuadPort DSE device). All ports read 0s,
then Port 1 writes 1s to all memory locations using MIA, then all ports read
1s. MIA read0_write1_read1 (MIA_r0w1r1).
Up count from 0 to 64K. All ports read 1s, then Port 1 writes 0s, then all ports
read 0s (MIA_r1w0r0).
Down count from 64K to 0. MIA_r0w1r1.
Down count MIA_r1w0r0.
Read all 0s.
Port 1 write all zeros to memory using March2 Algorithm (M2A).
Up count M2A_r0w1r1.
Up count M2A_r1w0r0.
Down count M2A_r0w1r1.
Description
Description
CY7C04312BV
CY7C04314BV
CY7C0430BV
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