LTM9005IV-AB#PBF Linear Technology, LTM9005IV-AB#PBF Datasheet - Page 16

• Manufacturer Part Number: LTM9005IV-AB#PBF
• Manufacturer: Linear Technology

Specifications of LTM9005IV-AB#PBF

• Lead Free Status / RoHS Status: Compliant

LTM9005
applicaTions inForMaTion
Custom matching networks can be designed using the port
impedance data listed in Table 2. This data is referenced
to the LO pin with no external matching.
Table 2 LO Input Impedance vs Frequency
LO Input Overload
Text to come.
Reference Operation
The LTM9005 includes an internal voltage reference that
is internally bypassed. An external reference can be used
or the internal reference can be configured for two pin
selectable input ranges. Tying the SENSE pin to V
the default range; tying the SENSE pin to 1.5V selects a
3dB lower range.
Other voltage ranges in-between the pin selectable ranges
can be programmed. An external reference can be used by
applying its output directly or through a resistive divider
16
FREQUENCY
(MHz)
1200
1500
1800
2200
2600
3000
3500
4000
4500
5000
300
500
700
900
50
IMPEDANCE
80.5 – j41.9
11.8 – j10.1
18.8 + j10.9
35.0 + j27.4
72.9 + j19.3
70.0 – j12.6
55.0 – j17.0
82.1 – j13.9
69.0 – j30.1
43.7 – j13.2
36.4 + j19.8
10.0 – j326
47.8 – j9.7
53.6 – j1.9
66.7 + j0.7
INPUT
0.991
0.820
0.632
0.474
0.350
0.241
0.196
0.167
0.102
0.039
0.143
0.263
0.290
0.154
0.271
MAG
S11
ANGLE
–155.9
–107.5
DD
–17.4
–99.2
151.8
100.8
–26.1
–64.3
–97.2
–26.8
–17.4
–43.5
111.6
31.3
2.1
selects
to SENSE. It is not recommended to drive the SENSE pin
with a logic device. The SENSE pin should be tied to the
appropriate level as close to the converter as possible. If
the SENSE pin is driven externally, note that this pin is
filtered internally with a 50Ω series resistor and a 0.1µF
capacitor to ground.
ADC Clock Input
The CLK input can be driven directly with a CMOS or TTL
level signal. A sinusoidal clock can also be used along with a
low-jitter squaring circuit before the CLK pin (Figure 8).
The noise performance of the ADC can depend on the
clock signal quality as much as on the analog input. Any
noise present on the CLK signal will result in additional
aperture jitter that will be RMS summed with the inherent
ADC aperture jitter.
In applications where jitter is critical, use as large an
amplitude as possible. Also, if the ADC is clocked with a
sinusoidal signal, filter the CLK signal to reduce wideband
noise and distortion products generated by the source.
Figure 9 and Figure 10 show alternatives for converting a
differential clock to the single-ended CLK input. The use
of a transformer provides no incremental contribution
SINUSOIDAL
Figure 8. Sinusoidal Single-Ended CLK Driver
CLOCK
INPUT
50Ω
4.7µF
0.1µF
1k
1k
NC7SVU04
FERRITE
0.1µF
BEAD
CLK
SUPPLY
CLEAN
LTM9005
9005 F08
9005p