LTM9005IV-AB#PBF Linear Technology, LTM9005IV-AB#PBF Datasheet - Page 19

• Manufacturer Part Number: LTM9005IV-AB#PBF
• Manufacturer: Linear Technology

Specifications of LTM9005IV-AB#PBF

• Lead Free Status / RoHS Status: Compliant

applicaTions inForMaTion
Table 4. MODE Pin Function
Overflow Bit
When OF outputs a logic high the converter is either over-
ranged or underranged.
Output Clock
The ADC has a delayed version of the CLK input available
as a digital output, CLKOUT. The falling edge of the CLKOUT
pin can be used to latch the digital output data.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
to the same supply that powers the logic being driven.
For example, if the converter drives a DSP powered by a
1.8V supply, then OV
supply.
OV
to the V
voltage from GND up to 1V and must be less than OV
The logic outputs will swing between OGND and OV
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF . The
data access and bus relinquish times are too slow to allow
the outputs to be enabled and disabled during full speed
operation. The output Hi-Z state is intended for use during
long periods of inactivity.
Shutdown Modes
The LTM9005 provides several levels of shutdown. The
mixer, both amplifiers and the ADC can all be shut down
independently. Furthermore, the ADC may be placed in
DD
MODE PIN
1/3V
2/3V
can be powered with any voltage from 500mV up
V
0
DD
DD
DD
DD
of the part. OGND can be powered with any
OUTPUT FORMAT
2’s Complement
2’s Complement
Straight Binary
Straight Binary
DD
should be tied to that same 1.8V
CLOCK DUTY CYCLE
DD
, should be tied
STABILIZER
Off
On
Off
On
DD
DD
.
.
shutdown or nap modes to conserve power. Connecting
ADCSHDN to GND results in normal operation. Connecting
ADCSHDN to V
which powers down all circuitry including the reference
and the ADC typically dissipates 1mW. When exiting
sleep mode, it will take milliseconds for the output data
to become valid because the reference capacitors have to
recharge and stabilize. Connecting ADCSHDN to V
OE to GND results in nap mode and the ADC typically dis-
sipates 30mW. In nap mode, the on-chip reference circuit
is kept on, so that recovery from nap mode is faster than
that from sleep mode, typically taking 100 clock cycles. In
both sleep and nap modes, all digital outputs are disabled
and enter the Hi-Z state.
Amplifier Shutdown
When the ADC is in sleep or nap mode, it is recommended
to shut down both the first and second amplifiers using
their respective shutdown pins, AMP1SHDN and AMP-
2SHDN. Connecting AMPSHDN to GND results in normal
operation. Connecting AMP1SHDN to V
amplifier preceding the SAW filter and connecting AMP-
2SHDN to V
filter. It is recommended to tie AMP1SHDN, AMP2SHDN
and ADCSHDN together and control with 3V logic.
Mixer Enable Interface
The mixer is enabled and shut down differently than the
other functions in the LTM9005. The voltage necessary to
turn on the mixer is 2.7V. To disable the mixer, the enable
voltage must be less than 0.3V. If the EN pin is allowed
to float, the mixer will tend to remain in its last operating
state. Thus it is not recommended that the enable function
be used in this manner. If the shutdown function is not
required, then the EN pin should be connected directly
to V
Supply Sequencing
The V
amplifiers. The V
Each V
bypassed. The mixer, both amplifiers and the ADC are
separate integrated circuits within the LTM9005; however,
there are no supply sequencing considerations beyond
CC1
CC
.
CC
pins provide the supplies to the mixer and both
pin is brought out separately and internally
CC3
DD
disables the amplifier following the SAW
DD
and OE to V
pin provides the supply to the ADC.
DD
results in sleep mode,
LTM9005
CC2
disables the
19
DD
and
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